Oracle International Corporation

Claire Shih

Chandan Shantharaj

Mamata Godthi

A method for designing an integrated circuit. The method may include obtaining a register-transfer level (RTL) file for the integrated circuit. The RTL file may include hardware description language code that describes various modules for the integrated circuit. The method may further include selecting, within the RTL file, various state elements having a predetermined clock skew. The method may further include associating, in response to selecting the state elements, the state elements with a predetermined clock header. The method may further include generating a gate-level netlist using the RTL file. The state elements may be assigned to the predetermined clock header in the gate-level netlist. The method may further include generating, using the gate-level netlist, a clock network for the integrated circuit. The state elements in the clock network may have the predetermined clock skew.

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Santa Clara, CA, United States of America

Claire Shih