Airbus Operations (s.a.s.)

Claire Pagetti

Victor Jegu

Frédéric Aspro

Frédéric Boniol

A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.

Method and device for loading and executing instructions with deterministic cycles in a multicore avionic system having a bus of which the access time is not predictable

Growing community of inventors

Toulouse, France

Claire Pagetti