Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (Crolles 2) Sas

Commissariat a L'energie Atomique

Centre National De La Recherche Scientifique

Stmicroelectronics Gmbh

Stmicroelectronics (Rousset) Sas

Claire Fenouillet-Beranger

Philippe Coronel

Pascal Fonteneau

Fabrice Nemouchi

Perrine Batude

Stéphane Denorme

Benoit Mathieu

Claire Gallon

Maud Vinet

Sorin Ioan Cristoloveanu

Laurent Brunet

Yohann Solaro

Nicolas J Loubet

Qing Liu

Shay Reboh

Frank Fournel

Sébastien Kerdiles

Olivier Thomas

Elisa Vianello

Aomar Halimaoui

Jean-Charles Barbe

Sylvain Barraud

Bernard Previtali

Heimanu Niebojewski

Pablo Acosta Alba

Olivier Rozeau

François Andrieu

Emmanuel Richard

Frédéric-Xavier Gaillard

Pierre Perreau

Rémy Gassilloud

Fabien Deprat

Sylvian Barraud

A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.

Method for manufacturing a microelectronic device

A connection structure for microelectronic device with superposed semi-conductor layers including a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, the connection structure further including a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.

Internal via with improved contact for upper semi-conductor layer of a 3D circuit

A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.

Integrated circuit having a plurality of active layers and method of fabricating the same

Fabrication of an integrated circuit comprising:

Semiconductor and metal alloy interconnections for a 3D circuit

A method for making a FET transistor, including the following steps:

Method of fabrication of a FET transistor having an overlapped gate

Method for fabricating transistors for an integrated 3D circuit, comprising:

Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit

Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

Device with transistors distributed over several superimposed levels integrating a resistive memory

A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

SOI integrated circuit equipped with a device for protecting against electrostatic discharges

This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b) providing a second structure successively including a substrate, an active layer, an intermediate layer, a first semiconducting layer and a porous second semiconducting layer; c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer; d) removing the substrate of the second structure so as to expose the active layer; e) adding dopants to the first semiconducting layer or to the active layer; f) irradiating the first semiconducting layer by a pulse laser so as to thermally activate the corresponding dopants.

Fabrication method of a stack of electronic devices

Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor a second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.

Superimposed transistors with auto-aligned active zone of the upper transistor

Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.

Method for producing interconnections for 3D integrated circuit

This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer; a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device; b) bombarding the polycrystalline semiconductor layer by a beam of species configured to form an amorphous part and to preserve a superficial polycrystalline part; c) bonding the first and second structures; d) removing the second substrate of the second structure; e) introducing dopants into the amorphous part, through the exposed active layer; f) thermally activating the dopants by recrystallization of the amorphous part.

This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.

A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.

Manufacturing of self aligned interconnection elements for 3D integrated circuits

The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

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Voiron, France

Claire Fenouillet-Beranger