Intel Corporation

Clair C Webb

Mark T Bohr

Tahir Ghani

Annalisa Cappellani

Abhijit Jayant Pethe

Harry Gomez

Brian S Doyle

Mark L Doczy

Uday Shah

Kaan Oguz

Charles C Kuo

David L Kencke

Satyarth Suri

Peter D MacWilliams

Robert L Farrell

Jose A Maiz

Jeffrey E Smith

William M Holt

Glen R Wagner

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Gate contact structure over active gate and method to fabricate same

Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same

An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

N-p butting connections on SOI substrates

A device for protecting an integrated circuit (IC) against electrostatic discharge (ESD) includes a self-triggered silicon controlled rectifier (STSCR) coupled across the internal supply potentials of the integrated circuit. The STSCR exhibits a snap-back in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. The STSCR comprises a pnpn semiconductor structure which includes a n-well disposed in a p-substrate. A first n+ region and a p-type region are both disposed in the n-well. The n+ and p-type regions are spaced apart and electrically connected to form the anode of the SCR. The ESD protection device also includes diode clamps between the periphery and internal power supply lines, and a novel well resistor which provides a distributed resistance further protecting sensitive output buffer circuitry.

Electrostatic discharge protection circuit

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

Cache subsystem for microprocessor based computer system with

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

Cache memory integrated circuit for use with a synchronous central

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Aloha, OR, United States of America

Clair C Webb