Motorola Corporation

International Business Machines Corporation

Freescale Semiconductor,inc.

Cindy Reidsema Simpson

Matthew Thomas Herrick

Joseph Edward Varsik

Thomas H Baum

Luis Jesus Matienzo

James Derek Legg

Gregory S Etherington

Logan L Simpson

Olubunmi O Adetutu

Robert W Fiordalice

Mohammed Rabiul Islam

Dean J Denning

Hsing H Tseng

Ajay Jain

Ramnath Venkatraman

Cristiano Capasso

Gregor Braeckelmann

Rina Chowdhury

Marijean E Azrak

Robert Douglas Mikkola

Edward Acosta

David Moralez Pena

Brett Caroline Baker

Cindy Kay Goldberg

An electroplating system () and process makes electrical current density across a semiconductor device substrate () surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (and) reduce the electrical current density near the edge of the substrate (). By reducing the current density near the edge of the substrate (), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (). The system can also be modified so that the material that plates on electrical current density modifier portions () of structures () can be removed without having to disassemble any portion of the head () or otherwise remove the structures () from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Process for depositing a layer of material on a substrate

Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.

Plated metal transistor gate and method of formation

An electroplating system ( ) and process makes electrical current density across, a semiconductor device substrate ( ) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers ( and ) reduce the electrical current density near the edge of the substrate ( ). By reducing the current density near the edge of the substrate ( ), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate ( ). The system can also be modified so that the material that electrical current density modifier portions ( ) on structures ( ) can be removed without having to disassemble any portion of the head ( ) or otherwise remove the structures ( ) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

In one embodiment, a conductive interconnect (,) is formed in a semiconductor device by depositing a dielectric layer (,) on a semiconductor substrate (,). The dielectric layer (,) is then patterned to form an interconnect opening (,). A tantalum nitride barrier layer (,) is then formed within the interconnect opening (,). A catalytic layer (,) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (,). A layer of electroless copper (,) is then deposited on the catalytic layer (,). A layer of electroplated copper (,) is then formed on the electroless copper layer (,), and the electroless copper layer (,) serves as a seed layer for the electroplated copper layer (,). Portions of the electroplated copper layer (,) are then removed to form a copper interconnect (,) within the interconnect opening (,).

Interconnect structure in a semiconductor device and method of formation

A method for electroplating a copper layer (,) over a wafer (,) powers a cathode of an electroplating system (,) in a manner that obtains improved copper interconnects. A control system (,) powers the cathode of the system (,) with a mix of two or more of: (i) positive low-powered DC cycles (,or,); (ii) positive high-powered DC cycles (,or,); (iii) low-powered, pulsed, positive-power cycles (,or,); (iv) high-powered, pulsed, positive-powered cycles (,or,); and/or (v) negative pulsed cycles (,or,). The collection of these cycles functions to electroplate copper or a like metal (,) onto the wafer (,). During electroplating, insitu process control and/or endpointing (,or,) is performed to further improve the resulting copper interconnect.

Method for forming a copper layer over a semiconductor wafer

An interconnect (,) is formed overlying a substrate (,). In one embodiment, an adhesion/barrier layer (,), a copper-alloy seed layer (,), and a copper film (,) are deposited overlying the substrate (,), and the substrate (,) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (,), a seed layer (,), a conductive film (,), and a copper-alloy capping film (,) are deposited over the substrate (,) to form an interconnect (,). The deposition and annealing steps can be performed on a common processing platform.

Method for forming a semiconductor device

A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method is ideal for plating three-dimensional materials such as cone-shaped connectors used in electronic circuit packages.

Method for photoselective seeding and metallization of three-dimensional materials

A method for selectively metallizing one or more through-holes, other openings (such as slots), or edges of an electronic circuit package comprising the steps of forming a layer of seeding solution on a drilled surface of a substrate of interest exposing this layer to light of appropriate wavelength, through a mask that does not completely cover the through-holes or openings and thereby results in the formation of metal seed on regions of the substrate surface corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method yields plated through-holes or other openings, each of which can accommodate multiple wires, rather then the traditional one wire per through-hole.

Method for circuitizing through-holes by photo-activated seeding

An electroplating system (,) and process makes electrical current density across a semiconductor device substrate (,) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (,and,) reduce the electrical current density near the edge of the substrate (,). By reducing the current density near the edge of the substrate (,), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (,). The system can also be modified so that the material that electrical current density modifier portions (,) on structures (,) can be removed without having to disassemble any portion of the head (,) or otherwise remove the structures (,) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Process for depositing a layer of material over a substrate

Method for photoselective seeding and metallization of three-dimensional

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Austin, TX, United States of America

Cindy Reidsema Simpson