Globalfoundries Inc.

Advanced Micro Devices Corporation

Ciby Thuruthiyil

Jung-Suk Goo

Zhi-Yuan Wu

Sushant S Suryagandh

Bhanwar Singh

Ramkumar Subramanian

Judy Xilin An

Philip A Fisher

Ali Icel

Kaveri Mathur

John Vincent Faricelli

Vineet Wason

Sriraaman Sridharan

Venkat Ramasubramanian

An approach for methodology enabling a verification of IC designs that compensates for degraded performance due to a physical placement, particularly a stacked physical placement is disclosed. A set of stacked devices from a plurality of devices in an IC design is determined. One or more instance parameters indicating a physical placement of a device in the set is determined. A compensation metric indicating one or more electrical characteristics of a device in the set is determined based on the one or more instance parameters.

Method for selectively modeling narrow-width stacked device performance

A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.

Method and apparatus for simulating gate capacitance of a tucked transistor device

In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET.

Test structure for determining gate-to-body tunneling current in a floating body FET

According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example. sizes and locations of semiconductor devices on semiconductor dies.

Method for robust statistical semiconductor device modeling

In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at least three unique body-tied FET structures, determining at least three unique relationships between the at least three unique gate-to-body currents and at least three gate-to-body current density components for the at least three unique body-tied FET structures, and utilizing those at least three unique relationships to determine the at least three gate-to-body current density components; wherein one of the gate-to-body current density components is used to determine the gate-to-body current for the floating body FET. In one embodiment, a test structure implements a method for determining a gate-to-body current in a floating body FET. The determined gate-to-body current may be used to predict hysteresis in the floating body FET.

Method and test system for determining gate-to-body current in a floating body FET

According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.

Method for quality assured semiconductor device modeling

Real-time analysis and control of a semiconductor silicidation process. The architecture includes system and methods for monitor and control of a silicidation process during rapid thermal anneal. An FTIR system analyzes selected and/or random regions where silicidation is occurring, and signals the process control system to control the process according to the status of the analyzed silicide formations.

Monitor and control of silicidation using fourier transform infrared scatterometry

A complementary metal oxide semiconductor (CMOS) fabrication process. The process comprises creating a polysilicon layer having a first thickness for a transistor gate area and a second thickness for a fuse area. The first thickness is greater than the second thickness, wherein most of the polysilicon in the fuse area will react with a metal layer to form polysilicide during a rapid thermal anneal (RTA) process.

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Fremont, CA, United States of America

Ciby Thuruthiyil