United Microelectronics Corp.

National Cheng-Kung University

Ite Tech. Inc.

Chyou-Hsiung Hwang

Jar-Ferr Yang

Cheng-Wang Huang

Zhi-Hsien Chen

Jen-I Huang

Shih-Chang Hisa

A multimedia playing method is provided. First, N audio files selected by a user are received, wherein N&#x3e;0. Then, the memory space required for playing each of the N audio files for a predetermined time is respectively detected. Next, whether total memory space required by the N audio files is not smaller than a predetermined value is determined. If the total memory space required by the N audio files is not smaller than the predetermined value, the predetermined time is reduced and the step of respectively detecting the memory space required for playing each of the N audio files for the predetermined time is executed again. If the total memory space required by the N audio files is smaller than the predetermined value, an initial part of each of the N audio files to be played for the predetermined time is stored into the memory.

Multimedia playing method and apparatus using the same

An apparatus that provides data communication between universal asynchronous receiver/transmitter (UART) modules on a first IC chip of a chip set and associated transceivers on a second IC chip of the same chip set. The apparatus includes a first multiplexer/demultiplexer unit coupled by first buses to the UART modules, and a second multiplexer/demultiplexer unit coupled by second buses to the transceivers. A common bus is interconnected between the first multiplexer/demultiplexer unit and the second multiplexer/demultiplexer unit. A control unit selectively connects the common bus to one of the first buses and one of the second buses so as to connect one of the UART modules in the first IC chip to the associated transceiver in the second IC chip.

Apparatus for data communication between universal asynchronous

A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.

Two-dimensional inverse discrete cosine transform processor

Growing community of inventors

Hsinchu, Taiwan

Chyou-Hsiung Hwang