Taiwan Semiconductor Manufacturing Comp. Ltd.

Epistar Corporation

TSMC Solid State Lighting Ltd.

Chyi-Shyuan Chern

Chi-Ming Yang

Hsin-Hsien Wu

Zin-Chang Wei

Chin-Hsiang Lin

Chun-Lin Louis Chang

Jong-I Mou

Jun-Lin Yeh

Chih-Lung Lin

Jih-Jse Lin

Ming-Yu Fan

Jo-Fei Wang

Simon Su-Horng Lin

Soon Kang Huang

Volume Chien

Shao-Yen Ku

Chi-Chun Chen

Matt Yeh

Fang Wen Tsai

Shun Wu Lin

Ching-Hua Chiu

Yung-Chang Chen

Yu-Ming Lee

Hung-Cheng Chen

Huang Soon Kang

Ming-Hua Lo

Kuan-Hsiao Lin

Pin-Chieh Hu

Wen-Chang Peng

Hsiao-Pin Shih

Ming-Jun Wang

Yu Yuan Kuo

Ming-Te Mo

Yung-Hsin Yang

Ming-Shing Lee

Chu-Ching Tsai

Kun-Ku Hung

Ming-Da Guo

The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.

Optimizing light extraction efficiency for an LED wafer

An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Multi-zone temperature control for semiconductor wafer

A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.

Shadow mask assembly

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

N/P metal crystal orientation for high-K metal gate Vt modulation

An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case.

Slurry dispenser for chemical mechanical polishing (CMP) apparatus and method

A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.

Retainer ring

An electroplating system is provided. The system comprises a reaction tank, a tube, and a video bubble detector. The reaction tank, having a first diameter, contains a plating solution. The tube, connecting to the reaction tank, comprises an inflow tube and a branch, wherein the inflow tube inputs the plating solution into the reaction tank, and the branch has an enlarged part having the first diameter. The video bubble detector, mounted on the enlarged part of the branch, detects the presence of a bubble in the plating solution flowing through the branch.

Electroplating systems and methods

The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than &#x2212;1.4 volts.

Method of fabricating high-k metal gate devices

A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.

High selectivity etching process for metal gate N/P patterning

A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.

Systems and methods for detecting device-under-test dependency

Growing community of inventors

Taipei, Taiwan

Chyi-Shyuan Chern