Hitachi, Ltd.

Renesas Technology Corp.

Murata Manufacturing Co., Ltd.

Renesas Electronics Corporation

Hitachi Denshi Kabushiki Kaisha

Chushiro Kusano

Yasunari Umemoto

Isao Ohbu

Atsushi Kurokawa

Satoshi Sasaki

Yasuo Osone

Kenji Sasaki

Tomonori Tanoue

Tsutomu Kobori

Hirokazu Nakajima

Katsuhiko Mitani

Susumu Takahashi

Toshio Nakano

Akira Sasano

Hidetoshi Matsumoto

Hideyuki Ono

Tadaaki Hirai

Hiroyuki Nagai

Eiichi Maruyama

Yoshinori Imamura

Kazuhiro Mochizuki

Masami Ohnishi

Masao Yamane

Yu Hasegawa

Tomoyoshi Mishima

Masayoshi Kobayashi

Ken Tsutsui

Yuji Shirai

Eiichi Hase

Mitsuhiro Mori

Chiko Yorita

Satoru Konishi

Shizuki Nakajima

Makoto Kudo

Akishige Nakajima

Katsuhiko Higuchi

Satoshi Tanaka

Tsuneo Endo

Yasuo Ohsone

A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.

Semiconductor device and radio communication device

A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions, andeach having a first number (e.g., seven) of the unit transistors Q, and transistor formation regionsandeach having a second number (e.g., four) of the unit transistors Q. The transistor formation regionsandare located between the transistor formation regions, and, and the first number is larger than the second number.

In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.

Semiconductor device and manufacturing method thereof

A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions, andeach having a first number (e.g., seven) of the unit transistors Q, and transistor formation regionsandeach having a second number (e.g., four) of the unit transistors Q. The transistor formation regionsandare located between the transistor formation regions, and, and the first number is larger than the second number.

A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Heterojunction bipolar transistor and method for manufacturing the same, and power amplifier using the same

A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions, andeach having a first number (seven) of the unit transistors Q, and transistor formation regionsandeach having a second number (four) of the unit transistors Q. The transistor formation regionsandare located between the transistor formation regions, andand the first number is larger than the second number.

A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Semiconductor device and manufacturing method therefor

The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Qto Qand a second group of a protection circuit having a plurality of bipolar transistors.

Semiconductor protection device

In a semiconductor device using an emitter top heterojunction bipolar transistor having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. This allows reduction of base/collector junction capacitance per unit emitter area, whereby a semiconductor device having high power adding efficiency and high power gain suitable for a power amplifier can be realized. Further, in a multistage power amplifier including first and second amplifier circuits each having one or more of bipolar transistors, a bipolar transistor in the first amplifier circuit uses an emitter having a planar shape in a rectangular shape, and a bipolar transistor in the second amplifier circuit uses an emitter having a ring-like shape and a base electrode only on the inner side of the emitter.

Semiconductor device, manufacturing thereof and power amplifier module

A semiconductor device has a lattice-mismatched crystal structure including a semiconductor film formed on a substrate with an intervening buffer layer. The buffer layer has a plurality of layers, including first sublayers, or regions, in which an element that controls the lattice constant is provided in increasing mole fraction, and second sublayers, or regions, in which the lattice constant is maintained. The first sublayers and second sublayers are provided in alternating fashion. The resulting device has an increased electron mobility as compared with the prior art.

Lattice-mismatched crystal structures and semiconductor device using the

An electronic circuit is provided with a first field effect transistor and a second field effect transistor, in which a drain of the first field effect transistor connected to a source of the second field effect transistor. This electronic circuit inputs a first signal to a gate electrode of the first field effect transistor, inputs a second signal to a gate electrode of the second field effect transistor and outputs a signal from a drain of the second field effect transistor. This electronic circuit is a cascode circuit related to the current drivability of the second field effect transistor is set to be larger than the current drivability of the first field effect transistor, and there is an effect that third-order or higher order distortion characteristics of a cascode type or dual-gate circuit can be reduced.

Low-distortion cascode circuit

Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

Method of manufacturing a heterojunction bipolar transistor

2A heterojunction bipolar transistor is disclosed in which a region of a base layer which extends in the vicinity of the interface between the base layer and an emitter layer is doped with an impurity at a higher concentration than that in the inside of the base layer to thereby form a built-in field by which carriers injected from the emitter are caused to drift to the inside of the base layer. In the transistor having this structure, the current gain does not depend on the emitter area, and it is possible to obtain a large current gain with a small emitter area.

Heterojunction bipolar transistor

Growing community of inventors

Niiza, Japan

Chushiro Kusano