Zte Corporation

Shenzhen Tcl New Technology Co., Ltd.

Sanechips Technology Co., Ltd.

Chunyu Tian

Hui Ren

Yingwen Liang

Bing Han

Weisi Zhan

Qingyu Chen

Tiago Abreu

Lea Hwang Lee

Yuzhong Zhang

Chengyang Wu

Fan Song

Lihuang Li

Cong Qin

Kunkun Yang

A data encoding method includes, writing information bits into at least two cache blocks, where the cache blocks store parity bits corresponding to the information bits, and two adjacent bits of data of the parity bits are stored in different cache blocks; and performing low density parity check code (LDPC) encoding according to the information bits and the parity bits in the cache blocks.

Data encoding method, electronic device, and storage medium

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The present disclosure discloses a method and device for data transmission between register files. The method includes that: data in a source register file are read at a Stage i of a pipeline; and the read data are transmitted to a destination register file using an idle instruction pipeline. With the method of the present disclosure, data and mask information are transmitted using an idle instruction pipeline, without addition of extra registers for data and control information buffering, thus reducing logic consumption as well as increasing utilization of an existing functional unit.

Method and device for data transmission between register files

The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.

Device and method for implementing address buffer management of processor

Growing community of inventors

Shenzhen, China

Chunyu Tian