Montage Technology Co., Ltd.

Montage Technology (shanghai) Co., Ltd.

Chunyi Li

Qingjiang Ma

Zhongyuan Chang

Peng Wang

Gang Shan

Howard Chonghe Yang

Jie Dai

Zhijie Liu

Song Xu

Lanxin Zhang

Yufeng Qu

A method for querying in a candidate vector set candidate vectors similar to object vectors is disclosed, wherein the candidate vector set comprises a plurality of candidate vectors each being quantized as having a central vector portion and a residual vector portion, the method comprising: querying, a first number of candidate vector subsets that are closest to the object vector; generating and storing a plurality of common calculation results based on a set of central vector portions and a set of residual vector portions of candidate vectors of the first number of candidate vector subsets; generating and storing pre-calculation results based on the set of object vectors and the set of residual vector portion; and determining, a second number of candidate vectors that are similar to each object vector in the corresponding first number of candidate vector subsets based on the stored pre-calculation results and common calculation results.

Method and apparatus for querying similar vectors in a candidate vector set

The application discloses a device and a method for picking up top k values from N values. The method comprises: A) controlling a buffer to receive values into a data pool until the number of values in the data pool reaches the predetermined memory size; B) dividing the values in the data pool into a first portion and a second portion; C) discarding the values in the second portion and controlling the buffer to continue to receive values into the data pool; D) repeating steps B to C until the buffer has received all the N values; E) dividing the values in the data pool into the first portion and the second portion until the number of values in the first portion reaches k; and F) controlling the buffer to output the k values in the first portion as the top k values.

Device and method for picking up top k values

The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

Memory controller

The present application discloses a computing device and a neural network processor including the computing device. The computing device includes one or more columns of computing units arranged in an array, wherein at least one computing unit in each column comprises: an arithmetic parameter memory for storing one or more arithmetic parameters; an arithmetic logical unit (ALU) for receiving input data and performing computation on the input data using the one or more arithmetic parameters stored in the arithmetic parameter memory; and an address controller for providing an address control signal to the arithmetic parameter memory to control the storage and output of the one or more arithmetic parameters.

Computing device and neural network processor incorporating the same

The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.

Memory controller enabling dual-mode access to memory module

A voltage and timing calibration method used in a memory system. A memory controller adjusts timing and voltages of the controller and voltages of a memory buffer according to data returned by the buffer based on timing and voltages at a memory controller side of the buffer, to calibrate timing and voltages between the controller and controller side. According to data read by the buffer from a memory chip unit on the basis of timing and voltages at a memory chip side of the buffer, the controller adjusts the timing and voltage at the chip side and the voltage of the chip unit; or the buffer adjusts the timing and voltage at the chip side and the voltage of the chip unit, to calibrate the timing and voltage between the chip side and chip unit. Therefore, hardware resources of the buffer can be saved and the circuit can be simplified.

Voltage and timing calibration method used in memory system

A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals. When determining availability of currently allocated address information, the device requiring address allocation stores currently allocated address information, and modifies address allocation flag information to address information already allocated, thereby achieving address allocation for the devices.

Growing community of inventors

Shanghai, China

Chunyi Li