Taiwan Semiconductor Manufacturing Comp. Ltd.

Chunyao Wang

Chi On Chui

Yung-Cheng Lu

Tze-Liang Lee

Chung-Ting Ko

Sung-En Lin

Wei-Che Hsieh

Wan-Yi Kao

Bo-Cyuan Lu

Ching Yu Huang

Tai-Chun Huang

Chih-Tang Peng

Jr-Hung Li

Yung-Chih Wang

Hsin-Hao Yeh

Yu-Cheng Shiau

Chun-Ming Lung

Han-Chi Lin

Syun-Ming Jang Jang

Ming-Ching Chang

Ryan Chia-Jen Chen

Shu-Yuan Ku

Yuan-Ching Peng

Jiun-Ming Kuo

Ming-Jie Huang

Che-Lun Chang

Kun-Yu Lee

Hung Cheng Lin

Hung-Ju Chou

Fang-Yi Liao

Nung-Che Cheng

Shih-Hao Fu

Ting-Gang Chen

Chieh-Ping Wang

Yin Wang

Chun-Yi Chang

A semiconductor device structure and methods of forming the same are described. In some embodiments, the method includes forming a dielectric layer, which includes forming an as deposited layer using an atomic layer deposition process, which includes flowing a silicon source precursor into a process chamber at a first flow rate, flowing a carbon and nitrogen source precursor into the process chamber at a second flow rate, and flowing an oxygen source precursor into the process chamber at a third flow rate. A ratio of the first flow rate to the second flow rate to the third flow rate ranges between about one to one to eight and one to one to twelve, and the as deposited layer has a carbon concentration substantially greater than a nitrogen concentration. The method further includes annealing the as deposited layer in an environment including HO to form the dielectric layer.

Semiconductor device structure and methods of forming the same

A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.

Semiconductor patterning and resulting structures

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack formed over the substrate. The semiconductor device structure includes a spacer structure formed over a sidewall of the gate stack. The spacer structure includes a dielectric layer, a silicon rich layer, and a protection layer. The dielectric layer is formed between the gate stack and the silicon rich layer. The silicon rich layer is formed between the dielectric layer and the protection layer. A first atomic percentage of silicon in the silicon rich layer is greater than about 50%. The semiconductor device structure includes a source/drain structure formed over the substrate. The spacer structure is formed between the source/drain structure and the gate stack.

Semiconductor device structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate and a first epitaxial structure over the first fin structure. The semiconductor device structure also includes a second epitaxial structure over the second fin structure. The semiconductor device structure further includes a dielectric fin over the semiconductor substrate. The dielectric fin is between the first fin structure and the second fin structure. The dielectric fin has an inner portion and a protective layer. The protective layer extends along sidewalls and a bottom of the inner portion, and the protective layer has a dielectric constant higher than that of the inner portion.

Semiconductor device with fin structures

In an embodiment, a method includes: forming a photoresist over a target layer; performing a plasma-enhanced deposition process, the plasma-enhanced deposition process etching sidewalls of the photoresist while depositing a spacer layer on the sidewalls of the photoresist; patterning the spacer layer to form spacers on the sidewalls of the photoresist; and etching the target layer using the spacers and the photoresist as a combined etching mask.

Semiconductor device and method

A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Semiconductor device and method of manufacture

A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

Forming low-stress silicon nitride layer through hydrogen treatment

A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region, forming a dummy gate stack over the channel region of the semiconductor element, depositing a first spacer layer over sidewalls of the dummy gate stack, depositing a second spacer layer over the first spacer layer, wherein the second spacer layer includes at least one silicon sublayer and at least one nitrogen-containing sublayer, after the depositing of the second spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess, and after the etching, removing the second spacer layer.

Field-effect transistor device with gate spacer structure

A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Method of modulating stress of dielectric layers

A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

Gapfill structure and manufacturing methods thereof

A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

Semiconductor devices and methods of manufacture

As deposited, hard mask thin films have internal stress components which are an artifact of the material, thickness, deposition process of the mask layer as well as of the underlying materials and topography. This internal stress can cause distortion and twisting of the mask layer when it is patterned, especially when sub-micron critical dimensions are being patterned. A stress-compensating process is employed to reduce the impact of this internal stress. Heat treatment can be employed to relax the stress, as an example. In another example, a second mask layer with an opposite internal stress component is employed to offset the internal stress component in the hard mask layer.

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Zhubei, Taiwan

Chunyao Wang