Intel Corporation

Chunxiao Lin

Sai Luo

Xin Zhou

Tin-Fook Ngai

Yingzhe Shen

Li Shang

Chao Zhang

Hu Tiger Chen

Xiaocheng Zhou

Sun C Chan

Shanshan Zheng

Shanshan Zhang

Kang Zhao

Sun Chan

A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

Multicore memory data recorder for kernel module

Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system.

Bridging and integrating devices across processing systems

Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.

Partial vectorization compilation system

According to some embodiments, a communication modulemay be configured to transmit data packet traffic and a management modulemay be configured to shape the data packet traffic transmitted by the communication module. The management modulemay shape the data packet traffic by buffering data packets routed at different times to the communication modulebased on at least one power management factor.

Shaping data packet traffic

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Beijing, China

Chunxiao Lin