Semiconductor Manufacturing International (shanghai) Corporation

Chuntian Yu

Hao Ni

Yi Jin Kwon

Hong Yu

Guangyan Luo

Xiaoyan Liu

A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.

Memory decoding system

A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.

Memory device, related method, and related electronic device

The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.

Growing community of inventors

Shanghai, China

Chuntian Yu