Integrated Telecom Express, Inc.

Chunta Chen

Ming-Kang Liu

Chiihsin Kao

A circuit and method that optimizes and adapts the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. A high speed system can select either of a first or a second adaptation routine to handle changes in the bit and gain loadings of sub-channel carriers based on line disturbances or transmission change requests, based on which is most aptly suited to handle the particular change. In a preferred embodiment the resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

Dual mode bit and gain loading circuit and process

A circuit and method that optimizes a set up time and control of bit and energy loadings of data sub-channels in a multi-channel data transmission signal is disclosed. A time out period, or an iteration count are used to control a setup time. An initialization routine attempts to make appropriate loadings within such time out period or within an iteration count parameter. If it is unable to do so, a handoff is made to a second routine to complete the loadings. In a preferred embodiment the initialization routine calculates rough parameters, while the second routine finalizes the capacity calculations. Another aspect of the invention ensures that the initialization routine can be repeated at a later time to re-compute appropriate bit and energy loadings to ensure that significant changes caused by line disturbances or large data rate variations can be quickly accommodated. In a preferred embodiment the resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DPM implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

Method and circuit for controlling setup of multichannel system

A process for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The inventive process is preferably embodied in an microcode routine executable by a high speed digital signal processor. The routine monitors, analyzes and stores sub-channel signal-to-noise characteristics, determines theoretical bit capacity loadings, evaluates power performance margins, and optimizes sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. Alternatively, for a given power performance margin, the achieved data rate can be maximized. To achieve these results, a number of non-zero bit sub-channels (N.sub.CH) are remembered from iteration to iteration, which results in a more optimal loading of the sub-channels. A unique new approach is also disclosed for deciding which of the sub-channels should be disabled to have a zero bit loading. If adjustments to bit loadings are required to achieve a particular initial target rate, those sub-channels which will have the least effect on the overall system performance margin are adjusted first, so that compliance with system performance margin requirements is better achieved. In addition, an 'iteration criteria' count can be incorporated in the process to ensure that the initialization of sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

Method for configuring data and energy parameters in a multi-channel

A circuit for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (N.sub.CH) from iteration to iteration, which results in a more accurate loading of the sub-channels. If adjustments to bit loadings are required to achieve a particular initial target rate, the circuit first adjusts those sub-channels which will have the least effect on the overall system performance margin, so that compliance with system requirements is better achieved. In addition, an 'iteration criteria' count can be incorporated to ensure that the initialization of sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

Circuit for configuring data and energy parameters in a multi-channel

An ADSL transceiver includes a new circuit and various iterative initialization and fine tuning routines for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal. The routines quickly converge to a target data rate by first estimating a power margin, and generating a bounded interval that includes the target rate. Thereafter, a binary iterative portion of the routine takes over and effectuates a final convergence to the target rate. A new mechanism for determining useful sub-channels is also disclosed. The resulting routines are extremely useful in that they maximize a data rate for a given power margin, and conversely, maximize a power margin for a given data rate. Two variants of a fine tuning process are also disclosed, and both can be used in combination to maximize system performance. The circuits and routines are preferably implemented in the form of an integrated circuit or module that includes a digital signal processor (DSP) and associated memory running a permanent binary coded executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. In an alternative form, the DSP may include a RAM that is loaded with the initialization and fine tuning routines from a computer readable media such as a floppy disk, a hard disk, a magnetic tape, a CD-ROM or other non-volatile computer readable storage media. In another embodiment, the circuits and routines may be implemented in the form of a software modem operating directly on a user's machine instead of using a separate DSP and associated memory.

ADSL transceiver implemented with associated bit and energy loading

A circuit for optimizing and adapting the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The circuit preferably includes a high speed memory coupled to a digital signal processor running an executable routine for analyzing sub-channel signal-to-noise characteristics, determining theoretical bit capacity loadings, evaluating power performance margins, and optimizing initial and adaptive sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. The circuit keeps track of the number of non-zero bit sub-channels (N.sub.CH) from iteration to iteration, which results in a more accurate loading of the sub-channels. If adjustments to bit loadings are required to achieve a particular initial target rate, the circuit first adjusts those sub-channels which will have the least effect on the overall system performance margin, so that compliance with system requirements is better achieved. In addition, an 'iteration criteria' count can be incorporated to ensure that the initialization or adaptation of sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

Circuit for configuring and dynamically adapting data and energy

An adaptive process for optimizing the bit and energy configurations of data sub-channels in a multi-channel data transmission signal is disclosed. The inventive process is preferably embodied in one or more microcode routines executable by a high speed digital signal processor. A first routine initializes the transmission system, while a second routine adaptively changes system parameters as necessary to accommodate channel performance changes, varying target bit rates, etc. Both of the routines monitor, analyze and store sub-channel signal-to-noise characteristics, determine theoretical bit capacity loading, evaluates power performance margin, and optimize sub-channel configurations based on a series of iterative calculations intended to maximize the overall system power performance margin for any given target data rate. Alternatively, for a given power performance margin, the achieved data rate can be maximized. To achieve these results, a number of non-zero bit sub-channels (N.sub.CH) are remembered from iteration to iteration, which results in a more optimal loading of the sub-channels. A unique new approach is also disclosed for deciding which of the sub-channels should be disabled to have a zero bit loading. If adjustments to bit loadings are required to achieve a particular initial target rate, those sub-channels which will have the least effect on the overall system performance margin are adjusted first, so that compliance with system performance margin requirements is better achieved. In addition, an 'iteration criteria' count can be incorporated in the process to ensure that sub-channel loadings can be effectuated (at least to a very close order) in a predetermined and controlled fashion. The resulting bit/energy loadings can be adjusted to be fully compliant with applicable Discrete Multi-Tone (DMT) implementations of Asymmetric Digital Subscriber Loop (ADSL) protocols.

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Fremont, CA, United States of America

Chunta Chen