Alibaba Group Holding Limited

Chunsheng Liu

Zhibin Xiao

Minghai Qin

Arjun Chaudhuri

Dimin Niu

Wei Han

Yuan Xie

Tianchan Guan

Yuhao Wang

Yuan Gao

Xiaoxin Fan

Disclosed are systems and methods that determine whether instances of data (e.g., forward activations, backward derivatives of activations) that are used to train deep neural networks are to be stored on-chip or off-chip. The disclosed systems and methods are also used to prune the data (discard or delete selected instances of data). A system includes a hierarchical arrangement of on-chip and off-chip memories, and also includes a hierarchical arrangement of data selector devices that are used to decide whether to discard data and where in the system the data is to be discarded.

Hierarchical methods and systems for storing data

Vector-vector multiplication or matrix-matrix multiplication computation on computing systems can include computing a first portion of a vector-vector multiplication product based on a most-significant-bit set of a first vector and a most-significant-bit set of a second vector, and determining if the first portion of the vector-vector multiplication product is less than a threshold. If the first partial vector-vector multiplication product is not less than the threshold, a remaining portion of the vector-vector multiplication product can be computed, and a rectified linear vector-vector multiplication product can be determined for the sum of the first portion of the vector-vector multiplication product and the remaining portion of the vector-vector multiplication product. If the first portion of the vector-vector multiplication product is less than the threshold, computation of the remaining portion of the vector-vector multiplication product can be skipped and the rectified linear vector-vector multiplication product can be set to a zero scalar.

Vector-vector multiplication techniques for processing systems

The present disclosure relates to an accelerator for systolic array-friendly data placement. The accelerator may include: a systolic array comprising a plurality of operation units, wherein the systolic array is configured to receive staged input data and perform operations using the staged input to generate staged output data, the staged output data comprising a number of segments; a controller configured to execute one or more instructions to generate a pattern generation signal; a data mask generator; and a memory configured to store the staged output data using the generated masks. The data mask generator may include circuitry configured to: receive the pattern generation signal from the controller, and, based on the received signal, generate a mask corresponding to each segment of the staged output data.

Systolic array-friendly data placement and control based on masked write

Systems and methods are provided for testing many-core processors consisting of processing element cores. The systems and methods can include grouping the processing elements according to the dataflow of the many-core processor. Each group can include a processing element that only receives inputs from other processing elements in the group. After grouping the processing elements, test information can be provided in parallel to each group. The test information can be configured to ensure a desired degree of test coverage for the processing element that that only receives inputs from other processing elements in the group. Each group can perform testing operations in parallel to generate test results. The test results can be read out of each group. The processing elements can then be regrouped according to the dataflow of the many-core processor and the testing can be repeated to achieve a target test coverage.

Systems and methods for testing many-core processors

The present disclosure provides methods and systems for executing a neural network. The method includes: receiving a plurality of input vectors of input data; generating, among the plurality of input vectors, an estimation value associated with a subset of an input vector based on a weight vector of the activation function; determining whether the estimation value associated with the subset of the input vector satisfies a threshold condition; and determining an output of the activation function based on the estimation value.

Method and system for executing neural network

A method and an apparatus for scheduling commands in a virtual computing environment includes picking a command. It is determined whether the command is a synchronization command or a conditional command. A synchronization command is an independent command. A conditional command is a dependent command that depends on a synchronization command. In response to the command being determined as the synchronization command, a waiting queue is enabled for the command, the waiting queue storing conditional commands dependent on a running synchronization command. The command is dispatched to a processing engine.

Scheduling commands in a virtual computing environment

A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.

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San Mateo, CA, United States of America

Chunsheng Liu