Intel Corporation

Chunlin Liang

Brian S Doyle

Gang Bai

Jun-Fei Zheng

Peng Cheng

Larry E Mosley

David B Fraser

Xiao-Chun Mu

Siddhartha Das

Robert S Chau

Brian E Roberds

Qi-De Qian

John P Barnak

Chun Mu

Xiao Chun Mu

The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

Thermal conducting trench in a semiconductor structure

A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Complementary metal gate electrode technology

The invention relates to a method of forming a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the method includes filling a portion of the trench with a thermally conducting material and patterning a contact to the thermally conducting material. The invention also relates to a semiconductor device. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

Thermal conducting trench in a semiconductor structure and method for forming the same

A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Isolated junction structure and method of manufacture

An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.

MOSFET gate electrodes having performance tuned work functions and methods of making same

A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

High dielectric constant metal oxide gate dielectrics

A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and replacing those gate electrodes with a gate electrode structure having at least two layers of metal. In a further aspect of the present invention, complementary metal oxide semiconductor integrated circuits are fabricated by replacing n-channel transistor gate electrodes with gate electrodes having at least a first metal and a second metal, and further replacing the p-channel transistor gate electrodes with gate electrodes having a third metal and a fourth metal. The first and second metal combination includes, but is not limited to, TiN and Al. The third and fourth metal combination includes, but is not limited to, TaN and Ni; TaN and Pd; and TaN and Pt.

Integrated circuit with MOSFETS having bi-layer metal gate electrodes

Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Method of making MOSFET gate electrodes with tuned work function

A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Method for tuning a work function for MOSFET gate electrodes

A method is provided including attaching an encapsulant to an integrated circuit (IC), forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, attaching a first surface of the substrate to the encapsulant so that the substrate is connected to the IC, attaching an electrical element to a second surface of the substrate, and electronically connecting the first surface of the substrate and the second surface of the substrate.

Flip-chip on flex for high performance packaging applications

Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes

Isolated junction structure for a MOSFET

Thermal conducting trench in a seminconductor structure and method for forming the same

A field effect transistor including a semiconductor substrate having a first doped region and a second doped region wherein the first doped region and the second doped region are defined by an implantation property. The implantation property of the first doped region has a first implantation characteristic and the implantation property of the second doped region has a second implantation characteristic, and the first implantation characteristic are different from the second implantation characteristic.

Growing community of inventors

San Jose, CA, United States of America

Chunlin Liang