Qualcomm Incorporated

Intel Corporation

Chunlei Shi

Jongrit Lerdworatawee

Thomas R Toms

Boris Andreev

Yu Pu

Justin Joseph Rosen Gagne

Chenchang Zhan

Seyed Mahmoudreza Saadat

Lew G Chua-Eoan

Hua Guan

Seong-Ook Jung

Christopher Cooper Riddle

Sugato Mukherjee

Giby Samson

Kenneth David Easton

Kendrick Hoy Leong Yuen

Waleed Khalil

Sandeep Chaman Dhar

Liangguo Shen

Guolei Yu

James A Wilson

Mukesh Bansal

Shengyuan Li

Qadeer A Khan

Loc Nguyen

Yicheng Wan

Lew G Choa-Eoan

Christopher C c/o Qualcomm Incorporated Riddle

A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.

Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

Boost and LDO hybrid converter with dual-loop control

In certain aspects, a method for providing electrical stimulation includes transferring energy from a battery to an electrode to charge the electrode, and, after the electrode is charged, transferring energy from the electrode to the battery to discharge the battery. The energy transferred from the electrode to the battery may include a portion of the energy transferred from the battery to the electrode.

Bi-directional switching regulator for electroceutical applications

Disclosed is switching power supply that includes a pulse frequency modulation (PFM) mode of operation current feedback control. A reference current source is configured to output a reference current at one of several selectable levels. The level of the reference current may vary during operation of the current feedback control loop.

Switched mode power supply having a staircase current limit

A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

Area and power efficient switchable supply network for powering multiple digital islands

The present disclosure includes circuits that have a switching regulator and methods of operating the circuits. The switching regulator may receive a switching signal that has a switching frequency. The circuit also includes a monitor circuit to monitor the switching frequency, and includes a reconfigurable inductance coupled to an output of the switching regulator. The monitor circuit may change the reconfigurable inductance. The circuit includes an amplifier to receive an envelope tracking signal. An output of the amplifier is coupled to the output of the switching regulator to provide a power supply voltage. The circuit may further include a switching generator circuit to produce the switching signal for the switching regulator based on an output current of the amplifier. The monitor circuit may compare a frequency of the envelope tracking signal to the switching frequency of the switching signal and accordingly change the reconfigurable inductance.

Switching regulator circuits and methods with reconfigurable inductance

In one embodiment, a circuit comprises a charge pump. A gain control circuit is configured to detect an input voltage and generate a gain control signal to change a gain of the charge pump to maintain the output voltage of the charge pump in a voltage range. A voltage to frequency converter is configured to detect the input voltage and change a frequency of a frequency control signal applied to the charge pump based in the detected input voltage to maintain the frequency in a frequency range so that the output voltage of the charge pump is maintained in the voltage range.

Charge pumps having variable gain and variable frequency

In one embodiment, a circuit comprises a first load circuit coupled to a first input voltage. A current sinking circuit is coupled to an output of the first load circuit. A second load circuit is coupled to ground. A current sourcing circuit is coupled between a second input voltage and an output of the second load circuit. A charge-recycling circuit is coupled between the output of the first load circuit and the output of the second load circuit to provide current from the current sinking circuit to the output of the current sourcing circuit to reduce current through the current sourcing circuit. The charge-recycling circuit can be a charge pump.

Charge-recycling circuits

Embodiments described herein relate to an improved circuit technique in a rail-to-rail input stage circuit utilizing non-complementary differential pairs with bias control designed to maintain a constant transconductance 'gm' throughout an input common mode voltage range. The rail-to-rail input stage circuit comprises a first differential pair circuit, a level-shifted differential pair circuit coupled with the first differential pair circuit, and a constant transconductance generation circuit coupled with the level-shifted differential pair circuit. The constant transconductance generation circuit is configured to control the bias current conducting in the level-shifted differential pair circuit based on current conducting in the first differential pair circuit to maintain a constant transconductance in the rail-to-rail input stage circuit.

Rail-to-rail input stage circuit with constant transconductance

Exemplary embodiments are related to switching power converters. A switching power converter may comprise a plurality of control unit configured for average current mode control, wherein each control unit of the plurality comprises a dedicated proportional control unit. The switching power converter may further comprise an integrator coupled to each control unit of the plurality of control unit and configured to convey a signal to each control unit.

Average current mode control of multi-phase switching power converters

In one embodiment, a circuit comprises a first switching transistor and a second switching transistor. The first switching transistor and the second switching transistor are coupled in series between an input voltage and ground and having a common node therebetween to provide a switching output. A first switching circuit selective couples a gate of the first switching transistor to the input voltage and a first mid-level voltage supply. A second switching circuit selectively couples a gate of the second switching transistor to a second mid-level voltage supply and ground. A charge-recycling circuit is coupled to the gate of the first switching transistor, the gate of the second switching transistor, the first mid-level voltage supply, and the second mid-level voltage supply to selectively recycle charge between the first mid-level voltage supply and the second mid-level voltage supply.

Charge-recycling circuits including switching power stages with floating rails

The present disclosure includes programmable snubber circuits and methods. In one embodiment, a circuit is configured between first and second power supply terminals. A programmable snubber circuit may be configured between the first and second power supplies to reduce ringing on the power supplies. In one embodiment, the circuit is a switching regulator and the power supply terminals are internal power supply terminals. The snubber circuit may be programmed to reduce ringing caused by switching currents through parasitic inductances in a package.

Programmable snubber circuit

A method and apparatus for optimizing a light emitting diode (LED) operation range is provided. The method comprises the steps of: turning on at least one LED; and then measuring an anode voltage of the at least one LED; then measuring a cathode voltage of the at least one LED. Once the measurements are completed, a forward voltage of the at least one LED is calculated. After the calculation, the at least one LED is turned off and a power multiplexer switch threshold is set for that LED based on the measured anode and cathode voltages.

Method and apparatus for LED forward voltage measurement for optimum system efficiency

In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

System and method of silicon switched power delivery using a package

An improved rail-to-rail (R-R) input stage circuit with dynamic bias control is described. Input stage circuit includes a differential pair circuit, a level shifted differential pair and a bias control circuit. The differential pair circuit and the level shifted differential pair are of same type, non-complementary MOS devices. In exemplary embodiments, a first and a second bias control circuits dynamically control the bias current of the level shifted differential pair and the bias current of the differential pair circuit, respectively, in response to the input common mode voltage of the rail-to-rail input stage circuit. First and second bias control circuits maintain the output impedance of the R-R input stage circuit at a desired level, as the R-R input stage circuit operates outside the input common mode voltage range supported by the level shifted differential pair and the differential pair circuit, respectively. Further exemplary embodiments include a first and a second gm control circuits. Gm control circuits maintain the transconductance of the R-R input stage circuit substantially constant over the entire input common mode voltage range of the R-R input stage circuit.

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San Diego, CA, United States of America

Chunlei Shi