Qualcomm Incorporated

Intel Corporation

Chunhui Mei

Subramaniam M Maiyuran

Varghese George

Vineet Goel

Dipankar Das

Naveen K Mellempudi

Jorge E Parra

Chandra S Gurram

Yan Li

Yongsheng Liu

Andrew Evan Gruber

Hong Jiang

Tao Wang

Alexei Vladimirovich Bourd

Ashutosh Garg

Lin Chen

Shubra Marwaha

Supratim Pal

Sasikanth Avancha

Wei Xiong

Jiasheng Chen

Durgesh Borkar

Dharma Teja Vooturi

Guofang Jiao

Maxim V Kazakov

Fangwen Fu

Gang Zhong

Donghyun Kim

Liang Li

Dhiraj D Kalamkar

Feng Ge

Usame Ceylan

Young In Yeo

Sumesh Udayakumaran

Sabareesh Ganapathy

Nariman Moezzi Madani

Yue Qi

Kristopher Wong

An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

Utilizing structured sparsity in systolic arrays

A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.

Dual pipeline parallel systolic array

Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.

Random sparsity handling in a systolic array

An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

Conversion hardware mechanism

A device for graphics processing includes a memory and at least one processor. The at least one processor is configured to generate image data for an image, fetch, for each two-dimensional matrix of multiple two-dimensional matrices of units of the image, a respective portion of the image data, and process each two-dimensional matrix of the multiple two-dimensional matrices based on the respective portion of the image data to generate pixel data for the image. To process each two-dimensional matrix of the multiple two-dimensional matrices, the at least one processor is configured to process multiple units arranged in a first two-dimensional matrix of the multiple two-dimensional matrices and process, after processing the multiple units arranged in the first two-dimensional matrix, multiple units arranged in a second two-dimensional matrix of the multiple two-dimensional matrices.

Non-linear processing of two-dimensional data

A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.

Constant multiplication with texture unit of graphics processing unit

Techniques for allowing for concurrent execution of multiple different tasks and preempted prioritized execution of tasks on a shader processor. In an example operation, a driver executed by a central processing unit (CPU) configures GPU resources based on needs of a first 'host' shader to allow the first shader to execute 'normally' on the GPU. The GPU may observe two sets of tasks, &#x201c;guest&#x201d; tasks. Based on, for example, detecting an availability of resources, the GPU may determine a &#x201c;guest&#x201d; task may be run while the &#x201c;host&#x201d; task is running. A second &#x201c;guest&#x201d; shader executes on a GPU by using resources that were configured for the first &#x201c;host&#x201d; shader if there are available resources and, in some examples, additional resources are obtained through software-programmable means.

Resource sharing on shader processor of GPU

A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.

Shader pipeline with shared data channels

A device includes a memory, and at least one programmable processor configured to determine, for each warp of a plurality of warps, whether a Boolean expression is true for a corresponding thread of each warp, pause execution of each warp having a corresponding thread for which the expression is true, determine a number of active threads for each of the plurality of warps for which the expression is true, sort the plurality of warps for which the expression is true based on the number of active threads in each of the plurality of warps, swap thread data of an active thread of a first warp of the plurality of warps with thread data of an inactive thread of a second warp of the plurality of warps, and resume execution of the at least one of the plurality of warps for which the expression is true.

GPU divergence barrier

Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.

Stochastic rasterization using enhanced stencil operations on a graphics processing unit (GPU)

In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.

Rendering graphics to overlapping bins

Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.

Output ordering of domain coordinates for tessellation

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San Diego, CA, United States of America

Chunhui Mei