Lg Display Co., Ltd.

ChungSik Kong

MiHee Shin

SungHyun Cho

Sungwook Chang

HongGyu Han

SeWan Lee

Juhnsuk Yoo

Byoungwoo Kim

Jaesung Yu

Mihee Shin

Jungsoo Park

Gyutae Kang

DongSoo Kim

Sewan Lee

Hojin Jung

A gate driver includes a plurality of stage groups each including a plurality of stages; and a plurality of start circuits each configured to output a start signal to each of the plurality of stage groups, wherein each of the plurality of start circuits outputs the start signal to an uppermost stage among the plurality of stages of each of the plurality of stage groups, so that an area of the gate driver can be reduced.

Gate driver having a plurality of start circuits and display device including the same

A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.

Gate driver and display panel having the same

A gate driving circuit and an image display device including the gate driving circuit are provided. In some embodiments of the present disclosure, the gate driving circuit includes a plurality of stages configured to sequentially and repeatedly output a plurality of scan pulses having different pulse widths in response to a gate control signal applied from a timing controller and the plurality of stages sequentially generate the plurality of scan pulses having different pulse widths and phase-delayed in response to three-phase clock pulses among the gate control signals and sequentially supply the plurality of scan pulses to gate lines of a display panel to selectively adjust a light emission period or a color display period for each red pixel, green pixel, and blue pixel, thereby improving image quality.

Gate driving circuit and image display device including ihe same

A gate driving circuit and a display device are disclosed. The gate driving circuit includes a shift register including a plurality of stages. Among the stages, an Nth stage includes a first transistor charging a Q node and a junction stress control circuit. A pull-up transistor using the Q node as a gate input controls an output signal of a stage output terminal. The junction stress control circuit includes a first, second, and third control transistors. The first control transistor, the second control transistor, the third control transistor, and the first transistor are connected to each other through a common node. The second control transistor adjusts junction stresses for the first control transistor and the first transistor by controlling a voltage of the common node. When the second control transistor is turned off, the third control transistor discharges the voltage of the common node.

Gate driving circuit and display device using the same

An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A n(n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage.

Gate driving circuit and electroluminescent display using the same

An electroluminescent display device includes sub-pixels connected to gate lines, and a gate driver configured to supply a scan signal to at least one of the gate lines, and including stages. One of the stages includes a QB-node regulation unit configured to charge a QB-node and a QP-node to turn-on voltage by using a first gate clock signal and a second gate clock signal, and a pull-down unit configured to output a turn-off voltage in response to a voltage of the QP-node. The QB-node regulation unit includes a QP-node control part configured to invert a phase of a voltage of a Q1-node and apply the voltage of the inverted phase to the QP-node, and a QB-node control part configured to bootstrap the QP-node. Accordingly, by employing the gate driver including the QB-node regulation unit that provides a stable voltage to the QB-node and the QP-node, the reliability of the gate driver can be improved, and the bezel of the electroluminescence display device can be reduced.

Gate driver and electroluminescence display device including the same

Disclosed herein is a liquid crystal display in which a hole is shared by thin-film transistors to thereby improve the aperture ratio. The liquid crystal display includes a substrate, a first thin-film transistor and a second thin-film transistor on the substrate. In the planarization film, a single hole is disposed to expose a portion of the source electrode or the drain electrode from each of the first thin-film transistor and the second thin-film transistor. Each of the first and second pixel electrodes is connected to the source electrode or the drain electrode of the first and second thin-film transistors via the single hole in the planarization film. Accordingly, the area of a black matrix is reduced and thus the aperture ratio of the liquid crystal displaycan be improved.

Liquid crystal display

Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.

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Paju-si, South Korea

ChungSik Kong