Samsung Electronics Co., Ltd.

Chungki Min

Gihwan Kim

Miso Shin

Boun Yoon

Donghoon Kwon

Chang-Sun Hwang

Geunwon Lim

Byoungho Kwon

Hyo-Jung Kim

Jongheun Lim

Sanghyeok Kim

Myeongan Kwon

Hansol Seok

Kieun Seo

Changsun Hwang

Kiseok Jang

Chanwook Seo

A semiconductor device includes a first substrate; circuit elements on the first substrate; lower interconnection lines electrically connected to the circuit elements; a second substrate on the lower interconnection lines; gate electrodes spaced apart from each other and stacked on the second substrate in a first direction that is perpendicular to an upper surface of the second substrate; channel structures penetrating through the gate electrodes, extending in the first direction, and respectively including a channel layer; through-vias extending in the first direction and electrically connecting at least one of the gate electrodes or the channel structures to the circuit elements; an insulating region surrounding side surfaces of through-vias; and a via pad between the through-vias and at least one of the lower interconnection lines in the first direction and spaced apart from the second substrate in a second direction, parallel to an upper surface of the second substrate.

Semiconductor devices and data storage systems including the same

A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.

Semiconductor device and electronic system including the same

A semiconductor device include; a substrate including a cell array region and a key region, a stack structure on the cell array region including vertically stacked electrodes, a dummy structure on the key region, a vertical channel structure penetrating the stack structure to connect the substrate, a dummy pillar penetrating the first dummy structure, an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar, and a capping layer on the key region and covering the key pattern.

Semiconductor device with key pattern and electronic system including same

A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure.

Semiconductor device, an electronic system including the same, and a method of manufacturing the semiconductor device

A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.

Gap-fill layers, methods of forming the same, and semiconductor devices manufactured by the methods of forming the same

Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.

Planarization method of a capping insulating layer, a method of forming a semiconductor device using the same, and a semiconductor device formed thereby

A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.

Three-dimensional semiconductor memory devices

Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

Growing community of inventors

Hwaseong-si, South Korea

Chungki Min