Samsung Electronics Co., Ltd.

Chunghee Kim

Minsu Kim

Ahreum Kim

Hyun Yeul Lee

Ha-Young Kim

Jintae Kim

Jiyoung Jung

Jaeseok Yang

Dae Seong Lee

Seungman Lim

Donggyun Kim

Sungkeun Park

Daekwon Kang

Younggook Park

Myungsoo Jang

A semiconductor device including first and second standard cells disposed in one of a first direction and a second direction intersecting the first direction, the first and second directions parallel to a substrate, and each of the first and second standard cells including a gate structure and an active region, and a filler cell adjacent to the first standard cell in the second direction and adjacent to the second standard cell in the first direction, wherein an output node of the first standard cell is connected to an input node of the second standard cell, an output active contact providing an output node of the first standard cell is connected to a wiring active contact among at least one dummy active contact included in the filler cell, and an input wiring providing an input node of the second standard cell is connected to the wiring active contact may be provided.

Semiconductor device and layout method therefor

A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.

Multi-bit flip-flop and integrated circuit including the same

An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

Electronic circuit including flip-flop using common clock

A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.

Individually coloring separated cell blocks in layout of integrated circuits

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Yongin-si, South Korea

Chunghee Kim