Elite Semiconductor Memory Technology, Inc

Vanguard International Semiconductor Corporation

Mosaid Technologies Corporation

Conversant Intellectual Property Management Incorporated

Chung-Zen Chen

Chung-Shan Kuo

Yang-Chieh Lin

Issac Y Chen

Robert Mao

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

An exemplary embodiment of the present disclosure provides a programming voltage generator for a nonvolatile memory device. The programming voltage generator comprises a power circuit, a detector, a switching circuit, a control signal generator, and a regulation circuit. The power circuit outputs a programming voltage according to a voltage control signal. The detector detects whether the programming voltage is larger than or equal to a breakdown voltage of the nonvolatile memory device, so as to output an indication signal. The switching circuit temporally drops the programming voltage according to the indication signal. The control signal generator generates a plurality of regulation control signals. The regulation circuit generates the voltage control signal according to the programming voltage and the regulation control signals.

Programmable voltage generator for nonvolatile memory device

A voltage regulator including an over-drive circuit and a control circuit is illustrated. The over-drive circuit receives a first voltage signal output from a sensing amplifier in a DRAM circuit, and regulates the first voltage signal according to an over-drive signal. The a control circuit electrically connected to the over-drive circuit receives a sense signal, and outputs the over-drive signal according to the sense signal, wherein the sense signal is asserted when a bit line in the DRAM circuit is sensed that an restoring and operation is performed. The over-drive signal goes down to a level of a second voltage signal from a current level thereof dependent on an external power merely when the sense signal is asserted but has not been asserted for a delay time, or otherwise, the over-drive signal is equal to the external power.

Voltage regulator

A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.

Voltage regulator circuit for generating a supply voltage in different modes

A circuit for providing a reference voltage includes a bandgap reference circuit, a first unity gain buffer coupled to the bandgap reference circuit, a first switch for coupling a second reference voltage node to a third reference voltage node, a first capacitor coupled to the third reference voltage node, a second switch for coupling the third reference voltage node to a fourth reference voltage node, and a second capacitor coupled to the fourth reference voltage node, wherein during operation a fourth reference voltage at the fourth reference voltage node decays when the second capacitor discharges. A control circuit provides control signals for intermittently operating the bandgap reference circuit and for controlling the switches to recharge the second capacitor after the fourth reference voltage decays a predetermined amount.

Intermittently activated bandgap reference circuit

The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.

Semiconductor memory device

Word line driver in a hierarchical NOR flash memory

A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.

Method for tracking delay locked loop clock

An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.

Over erase correction method of flash memory apparatus

A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.

Erase verification method of flash memory by selectively assigning deselected sectors

A voltage level shifter comprises a voltage adjustment circuit, an inverter, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second NMOS transistor. The voltage adjustment circuit is configured for receiving a first voltage and a second voltage and for generating an adjustment voltage. When the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.

Growing community of inventors

Hsinchu, Taiwan

Chung-Zen Chen