Nan Ya Technology Corporation

United Microelectronics Corp.

Inotera Memories, Inc.

Chung-Yuan Lee

Tzung-Han Lee

Shian-Jyh Lin

Pei-Ing Paul Lee

Chien-Li Cheng

Chung-Yu Wu

Sun-Chieh Chien

Chun-Yen Chang

Joe Ko

Zhibiao Zhou

Chen-Bin Lin

Hsu Chiang

Yaw-Wen Hu

Meng-Hung Chen

Hung-Chang Liao

Sheng-Hsiung Wu

Chih-Hao Cheng

Ming-Dou Ker

Chen-Chiu Hsue

Tieh-Chiang Wu

Jeng-Ping Lin

Chi-Fa Ku

Ding-Lung Chen

Shing-Ren Sheu

Jer-Chyi Wang

Sanpo Wang

Hsin-Huei Chen

Yu-Sheng Shu

Hung Chang Liao

Yi-Nan Chen

Hsien-Wen Liu

Chung-Lin Huang

Ming-Tzong Yang

Su Xing

Chih-Wei Huang

Chang-Rong Wu

Hun-Hsien Chang

Yuan-Hsun Wu

Te-Yin Chen

Chao-Sung Lai

Chia-Ming Yang

Chung-Peng Hao

Wei-Chi Lee

Yu-Lin Wang

Chien-Mao Liao

Sheng-Wei Yang

Hai-Han Hung

Tzung Han Lee

Chen-Chou Huang

Chi-Chang Shuai

En-Jui Li

Tzu-En Ho

Sheng-Tsung Chen

Yu-Chang Lin

Chen-Chiu Hsu

Tah-Te Shih

Wen-Sheng Liao

Chung Peng Hao

Hsing-Kan Peng

Yang-Ling Wu

Shian-Hau Liao

Chien-Chi Lee

Chih-How Chang

Ming Hung Lo

Yih-Ren Shao

Chun-Liang Hu

Chih-Yung Kang

Shih-Hsiung Chiu

Yao-Hsien Wang

Chen-Kang Wei

Ming Yean

Yi-Wei Chuang

Hsiao-Lung Chiang

Ming-Chi Chao

Yuan Ku Lan

Chin-Tien Yang

Yu-Sheng Hsu

A trim circuit for an e-fuse unit includes: a mirroring circuit for receiving an enable signal, when triggered by the enable signal, the mirroring circuit generating a driving voltage; and a driving transistor coupled to the mirroring circuit, in response to the driving voltage from the mirroring circuit, the driving transistor turning ON to generate a MOS current to an output node, wherein the output node is coupled to the e-fuse unit, and in response to the MOS current from the output node, the e-fuse unit is burned out.

Trim circuit for e-fuse

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

Semiconductor device

The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Mask set and method for fabricating semiconductor device by using the same

A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.

Memory unit, memory unit array and method of manufacturing the same

A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.

Semiconductor structure

A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Semiconductor device and manufacturing method therefor

A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si&#x2014;Ge layer, an epitaxial Si layer and a second strained Si&#x2014;Ge layer. The first strained Si&#x2014;Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si&#x2014;Ge layer. The second strained Si&#x2014;Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si&#x2014;Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.

Vertical PMOS field effect transistor and manufacturing method thereof

A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.

Semiconductor layout structure

A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

Method of patterning metal alloy material layer having hafnium and molybdenum

A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.

DRAM with dopant stop layer and method of fabricating the same

A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.

Vertical transistor for random-access memory and manufacturing method thereof

A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning

Growing community of inventors

Tao-Yuan, Taiwan

Chung-Yuan Lee