General Electric Company

Chung-Yih Ho

Daniel Arthur Staver

Juka Mikko Hakkarainen

Karl J Molnar

Nga Cheung Lee

Ertugrul Berkcan

Jerome Johnson Tiemann

Xianrui Huang

Michael James Hartman

Minfeng Xu

Timothy John Havens

Richard I Hartley

Donald Thomas McGrath

Kenneth B Welles, Ii

Bu-Xin Xu

Fathy F Yassa

Steven Ho-Chong Wong

Chi-Yuan Chin

A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

On-chip communication circuit and protocol for microcontroller-based

In the installation of a superconducting magnet for magnetic resonance imaging at a preselected position in a mobile van, preselected curvilinear magnetic segments are applied to preselected locations on the exterior of the magnet to counteract magnet inhomogeneities in the imaging bore which would otherwise occur because of magnetic material in the van structure.

Resonance imager mobile van magnetic field homogeneity shift compensation

Shift register having latch cell operable in serial-in/parallel-out and

A programmable data acquisition system including a plurality of input signal channels for receiving a respective input signal during a normal mode of operation is provided. Individual test circuits are used for selecting respective ones of the plurality of channels to receive predetermined reference signals during a test mode of operation while uninterruptedly providing the normal mode of operation in any remaining unselected channels in the data acquisition system. An analog-to-digital (A/D) converter system, such as delta-sigma modulators and decimation filters having a selectable decimation ratio, allows for supplying quantized electrical signals at a predetermined rate. The A/D converter is responsive to any signals carried in the plurality of signal channels as selected by the individual test circuits. A control unit allows for supplying respective control signals to the test circuits and to the converter system. The data acquisition system can further include at least one feedback generating circuit for generating a measurement signal supplied to a respective one of the signal channels. This allows the data acquisition system for interfacing with a zero-flux current sensor.

Programmable data acquisition system for collecting electrical power

An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard cell designs in a tessellation procedure. The array multiplier is laid out in accordance with one of particular tessellation patterns, which employ simpler and more regular patterns of interconnections between cells. Carry-save addition is used in combining partial product terms to avoid concatenating long ripple carry times.

Array multiplier adapted for tiled layout by silicon compiler

Apparatus for sensing linear displacement of an object between first and second locations along an axis is used to sense conditions that can be made to vary displacement of an object in accordance with the condition, such as temperature, pressure and rotary motion. A light beam projected along an incident light path to the object is reflected along a reflective light path by a reflector affixed to the object. A photo-sensor array in the reflective light path intercepts the reflected light beam and produces samples of the intensity of the reflected image at multiple positions along a line across the array. An imager coupled to the array converts the light samples to representative electrical samples. The resultant light intensity information is provided to an electronic processor which determines a first centroid of the reflected image when the object is at a first location and a second centroid when the object is at a second location, and employs the difference between the first and second centroids to determine the displacement of the object.

Optical sensing apparatus for detecting linear displacement of an object

A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.

Versatile data shifter with sticky bit generation capability

A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.

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Chavenay, France

Chung-Yih Ho