Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Yi Yu

Chi-Ming Chen

Chia-Shiung Tsai

Po-Chun Liu

Chih-Ming Chen

Chen-Hao Chiang

Szu-Yu Wang

Kuei-Ming Chen

Xiaomeng Chen

Yeur-Luen Tu

Han-Chin Chiu

Ru-Liang Lee

Rei-Lin Chu

Dun-Nian Yaung

Yeong-Jyh Lin

Ho-Yung David Hwang

Cheng-Te Lee

Hsing-Lien Lin

Ping-Yin Liu

Yuan-Chih Hsieh

Xin-Hua Huang

Hung-Ta Lin

Tsu-Hui Su

Min-Chang Ching

Chiao-Chun Hsu

Tzu-Hsuan Hsu

Chii-Ming M Wu

Ching I Li

Shih-Chang Liu

Cheng-Yuan Tsai

Chun-Feng Nieh

Chi-Hsin Lo

Tsung-Hsun Huang

Ching-Hung Wang

Chern-Yow Hsu

Ming Chyi Liu

Jung-Huei Peng

Chang-Ming Wu

Chen-Ming Huang

Hung-Hua Lin

Ya-Chen Kao

Eugene Chen

De-Yang Chiou

Sz-Fan Chen

Chang-Jen Hsieh

Chung-Chieh Hsu

Han-Jui Hu

Chin-Cheng Chang

Sheng-Hsun Lu

Chih-Hao Wang

Alexander Kalnitsky

Der-Chyang Yeh

Wen-Ting Chu

Cheng-Ta Wu

Shou-Gwo Wuu

Hung-Cheng Sung

Jiun-Lei Jerry Yu

Hsun-Chung Kuang

Wen-De Wang

King-Yuen Wong

Tsung-Yu Chen

Kai-Wen Cheng

Shih-Chi Fu

Chih-Wen Hsiung

Chih-Ping Chao

Kuo-Yin Lin

Kuo-Hwa Tzeng

Chih-Ta Wu

Martin Liu

Lung Yuan Pan

Da-Hsiang Chou

Ming-Chang Ching

Chris Hsieh

Che Ying Hsu

Jen-Cheng Liu

Kuo-Ming Wu

Lan-Lin Chao

Neng-Kuo Chen

Yuan-Tai Tseng

Feng-Jia Shiu

Yi-Shin Chu

Hua-Chou Tseng

Yuan-Hung Liu

Kuan-Chieh Huang

Chun-Jung Lin

Jen-Sheng Yang

Min-Ying Tsai

Gwo-Yuh Shiau

Yao-Chung Chang

Han-Ping Chen

Shih Wei Wang

Alex Hsu

Ming-Te Liu

Li-Wen Chang

Derek Lin

Tung-Ti Yeh

Hsieh Ching Pei

Tzu-Wei Yu

Various embodiments of the present disclosure are directed towards an integrated chip including a first transistor on a semiconductor substrate. The first transistor includes a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate. The first pair of source/drain regions comprise a first dopant. The diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant. A doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures.

Diffusion barrier layer for source and drain structures to increase transistor performance

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Rough buffer layer for group III-V devices on silicon

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Method to reduce breakdown failure in a MIM capacitor

In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first heating plate arranged within a processing chamber and a second heating plate arranged within the processing chamber vertically over the first heating plate. A first exhaust port is arranged within the processing chamber and a second exhaust port arranged within the processing chamber vertically over the first exhaust port. The first exhaust port is in communication with the first heating plate and is coupled to a first exhaust output. The second exhaust port is in communication with the second heating plate and is coupled to a second exhaust output. A first control element is configured to control a first exhaust pressure at the first exhaust port and a second control element is configured to control a second exhaust pressure at the second exhaust port.

Semiconductor tool having controllable ambient environment processing zones

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Source/drains in semiconductor devices and methods of forming thereof

In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.

Self-aligned dielectric liner structure for protection in MEMS comb actuator

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

3D trench capacitor for integrated passive devices

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Manufacturing method of semiconductor device

In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes introducing a first processing gas of an atomic layer deposition (ALD) process on the semiconductor substrate in a chamber; introducing a second processing gas of the ALD process on the semiconductor substrate in the chamber; creating an exhaust flow from the chamber; monitoring a concentration of the first processing gas of the ALD process in the exhaust flow; in response to the monitored concentration of the first processing gas of the ALD process in the exhaust flow, introducing a cleaning gas into the chamber.

Method of optimizing film deposition process in semiconductor fabrication by using gas sensor

A high electron mobility transistor (HEMT) includes a substrate; and a first semiconductor layer over the substrate. The HEMT further includes a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a band gap discontinuity with the first semiconductor layer, and at least one of the first semiconductor layer or the second semiconductor layer comprises indium. The HEMT further includes a top layer over the second semiconductor layer. The HEMT further includes a gate electrode over the top layer. The HEMT further includes a source and a drain on opposite sides of the gate electrode, wherein the top layer extends continuously from below the source, below the gate electrode, and to below the drain.

High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

In some embodiments, a method for forming a semiconductor device is provided. The method includes etching a substrate to form a recess within a surface of the substrate. An epitaxial material is formed within the recess, a capping structure is formed on the epitaxial material, and a capping layer is formed onto the capping structure. The capping layer laterally extends past an outermost sidewall of the capping structure. Dopants are implanted into the epitaxial material. Implanting the dopants into the epitaxial material forms a first doped region having a first doping type and a second doped region having a second doping type.

Capping structure to reduce dark current in image sensors

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Photolithography alignment process for bonded wafers

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

MIM capacitor with a symmetrical capacitor insulator structure

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Substrate loss reduction for semiconductor devices

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Hsin-Chu, Taiwan

Chung-Yi Yu