United Microelectronics Corp.

Au Optronics Corporation

Alpha Networks Inc.

Chung-Yi Chiu

Cheng-Han Tsao

Te-Wei Chan

Chieh-Wei Chen

Chih-Wei Kuo

Shih-Fang Hong

Bin-Siang Tsai

Wen-Hao Hsu

Da-Jun Lin

Fu-Yu Tsai

Sheng-Ju Ho

Yi-Pai Huang

Jenn-Jia Su

Chao-Hung Lin

Ting-Yi Cho

Kung-Ching Chu

Yen-Ting Chen

Chun-Lung Chen

Po-Kai Hsu

Peng-Bo Xi

Yen-Heng Huang

Tien-Lun Ting

Chia-Huei Lin

Li-Che Chen

Wen-Hsien Tseng

Hui-Min Wu

Chia-Hui Pai

Chao-Yuan Chen

Chung-Kai Chen

Te-Yuan Wu

Kuan-Yu Wang

Kun-Chen Ho

Chih-Haw Wang

Chang-Mao Wang

Kun-Che Hsieh

Wen-Wen Zhang

Ming-Chou Lu

Chin-Fu Lin

Ting-Jui Chang

Kuo-Chih Lai

Nien-Ting Ho

Hung-Chan Lin

Wei-Lun Hsu

Yung-Feng Cheng

Chin-An Tseng

Shih-Min Chou

Chun-Chi Yu

Yi-Yu Lin

Li-Han Chen

Wei-Yuan Cheng

Wei-Ming Hsiao

Chih-Wei Chang

Hui-Fang Kuo

Ting-Wei Su

Kuan-Ying Lai

Ching-Pei Lin

Dien-Yang Lu

Ya-Chieh Chen

Wei-Cyuan Lo

Hsin-Yu Hsieh

Szu-Yao Yu

Yi-Jen Huang

Te-Hsuan Chen

Shu-Yen Liu

Ming-Wei Chen

Chian-Ting Huang

Hsiu-Wu Wu

Guo-Xin Hu

Yuh-Kwei Chao

Min-Cheng Yang

Yeh-Sheng Lin

Chia-Wei Chen

Hsiao-Ying Yang

Po-kai Hsu

Yen-heng Huang

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

Semiconductor device and method for fabricating the same

A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.

Compound semiconductor device and fabrication method thereof

An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

MIM capacitor structure and fabricating method of the same

A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

Structure with photodiode, high electron mobility transistor, surface acoustic wave device and fabricating method of the same

An RRAM structure includes a substrate. A transistor is disposed on the substrate, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric layer covers the transistor. A drain contact plug is disposed within the interlayer dielectric layer and contacts the drain, and wherein an end of the drain contact plug protrudes from the interlayer dielectric layer. A metal interlayer dielectric layer is disposed on and contacts the interlayer dielectric layer. A resistive random access memory (RRAM) is disposed on the drain and within a first trench in the metal interlayer dielectric layer, wherein the RRAM includes a bottom electrode, a metal oxide layer and a top electrode, the drain contact plug contacts the bottom electrode, the bottom electrode contacts the metal oxide layer and the top electrode contacts the metal oxide layer. A metal layer is disposed within the first trench.

Resistive random access memory structure and fabricating method of the same

A training method of a semiconductor process prediction model, a semiconductor process prediction device, and a semiconductor process prediction method are provided. The training method of the semiconductor process prediction model includes the following steps. The semiconductor process was performed on several samples. A plurality of process data of the samples are obtained. A plurality of electrical measurement data of the samples are obtained. Some of the samples having physical defects are filtered out according to the process data. The semiconductor process prediction model is trained according to the process data and the electrical measurement data of the filtered samples.

Training method for semiconductor process prediction model, semiconductor process prediction device, and semiconductor process prediction method

An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

SOT MRAM structure and fabricating method of the same

A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

Gallium nitride device with field plate structure and method of manufacturing the same

A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Field effect transistor and fabrication method thereof

A memory device includes a substrate, a memory unit disposed on the substrate, a first spacer layer, and a second spacer layer. The memory unit includes a first electrode, a second electrode disposed above the first electrode, and a memory material layer disposed between the first electrode and the second electrode. The first spacer layer is disposed on a sidewall of the memory unit and includes a first portion disposed on a sidewall of the first electrode, a second portion disposed on a sidewall of the second electrode, and a bottom portion. A thickness of the second portion is greater than that of the first portion. The second spacer layer is disposed on the first spacer layer. A material composition of the second spacer layer is different from that of the first spacer layer. The bottom portion is disposed between the substrate and the second spacer layer.

Memory device

A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

Method of removing step height on gate structure

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

Manufacturing method of memory device

A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

Mask correction method, mask correction device for double patterning and training method for layout machine learning model

An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Optical proximity correction device and method

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Tainan, Taiwan

Chung-Yi Chiu