Promos Technologies, Inc

Chung-Yi Chen

Chih-Ping Chung

Hung-Kwei Liao

Chun-Nan Lin

A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Growing community of inventors

Jhonghe, Taiwan

Chung-Yi Chen