Taiwan Semiconductor Manufacturing Comp. Ltd.

Nan Ya Technology Corporation

Chung-Yen Chou

Chia-Shiung Tsai

Shih-Chang Liu

Ming-Chyi Liu

Lee-Chuan Tseng

Yuan-Tai Tseng

Sheng-De Liu

Ru-Liang Lee

Yuan-Chih Hsieh

Chih-Jen Chan

Che-Ming Chang

Fu-Ting Sung

Ching-Pei Hsieh

Kuo-Chi Tu

Yao-Wen Chang

Shih-Wei Lin

Wen-Chuan Chiang

Chih-Yang Pai

Po-ken Lin

Ming Chyi Liu

Fu-Chih Yang

Yung-Chang Chang

Chi-Ming Chen

Tieh-Chiang Wu

Hsin-Jung Ho

Hai-Han Hung

Shin-Yu Nieh

Xiao-Meng Chen

Teng-Wang Huang

Lung-Yuan Pan

Chia-Shiung Tsa

A semiconductor structure includes an Nmetal layer, a diffusion barrier layer over the Nmetal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Semiconductor structure, electrode structure and method of forming the same

An integrated chip comprising a memory cell is provided. The memory cell is disposed over a substrate and comprises a data storage layer between a top metal layer and a bottom metal layer. An etch stop layer overlies the top metal layer. An upper dielectric layer overlies the etch stop layer. Outer sidewalls of the etch stop layer, outer sidewalls of the upper dielectric layer, and outer sidewalls of the top metal layer are aligned. A top electrode overlies the memory cell. The top electrode directly contacts inner sidewalls of the top metal layer, inner sidewalls of the etch stop layer, and inner sidewalls of the upper dielectric layer.

Top electrode last scheme for memory cell to prevent metal redeposit

A method for forming a memory device is provided. The method including forming a memory cell stack over a substrate. The memory cell stack includes a bottom metal layer, a top metal layer, and a data storage layer disposed between the bottom metal layer and the top metal layer. The memory cell stack is patterned such that sidewalls of the data storage layer, sidewalls of the top metal layer, and sidewalls of the bottom metal layer are substantially aligned and are slanted at a non-zero angle. A top electrode is formed over the top metal layer.

A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Integrated circuit having a resistor layer partially overlapping endcaps

Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Manufacturing method of semiconductor structure

A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

Microelectromechanical systems (MEMS) structure to prevent stiction after a wet cleaning process

A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

Semiconductor arrangement and formation thereof

A method of manufacturing a semiconductor structure includes: providing a substrate; forming a first conductive layer having a first opening over the substrate; depositing a first dielectric layer over the first conductive layer and covering the first opening; forming a second conductive layer having a second opening over the first dielectric layer; depositing a second dielectric layer over the second conductive layer and covering the second opening; performing an etching operation through the second dielectric layer at the second opening and the first dielectric layer at the first opening to form a first via; and forming a first conductive structure in the first via.

Semiconductor device with integrated capacitor and manufacturing method thereof

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate and a gate element over the substrate. The gate element includes: a gate dielectric layer over the substrate; a gate electrode over the gate dielectric layer; and a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode. A manufacturing method of the same is also disclosed.

Semiconductor structure and manufacturing method of the same

A method for forming a memory device is provided. The method including forming a memory cell stack over a lower interconnect layer over a substrate, the memory cell stack includes a data storage layer over a bottom metal. A first dielectric layer is formed over the memory cell stack. A first masking layer is formed over the first dielectric layer. The first masking layer overlies a center portion of the first dielectric layer and leaves a sacrificial portion of the first dielectric layer uncovered. A first etch of the first dielectric layer is formed according to the first masking layer. An inter-metal dielectric (IMD) layer is formed over the memory cell stack. A top electrode is formed within the IMD layer over the memory cell stack. An upper interconnect layer is formed over the top electrode. The upper and lower interconnect layers comprise a different material than the top electrode.

Methods of manufacturing a thin film resistor with ends overlapped by interconnect pads

A semiconductor structure includes a capacitor including a first electrode and a second electrode disposed over and electrically insulated from the first electrode. The semiconductor structure also includes a first conductive via extending through the first electrode and contacting a planar surface of the first electrode. The semiconductor structure further includes a second conductive via extending through the second electrode and contacting a planar surface of the second electrode.

Growing community of inventors

Hsinchu, Taiwan

Chung-Yen Chou