Samsung Electronics Co., Ltd.

Kwang-youl Seo

Seoul National University

Chung-woo Kim

Soo-doo Chae

Jo-won Lee

Hee-soon Chae

Sang-hun Jeon

Jeong-Hee Han

Moon-kyung Kim

Ju-Hyung Kim

Eun-hong Lee

Hyun-Sang Hwang

Youn-seok Jeong

Yoon-Dong Park

Sang-Moo Choi

Sun-ae Seo

I-hun Song

Sang-Hun Jeon

Won-il Ryu

Woo-joo Kim

Ju-hyung Kim

In-sang Song

Byung-Gook Park

Moon-chul Lee

Byung-chul Kim

Jong-seok Kim

Eun-sung Lee

Sung-kyu Choi

Byong-man Kim

Sung-Kweon Baek

Tae-hyun Han

Se-wook Yoon

Joo-yeon Kim

Jung-hyun Lee

Wan-jun Park

Yong-Kyu Lee

Il-Han Park

Jae-woong Hyun

Sung-ho Park

Won-bong Choi

Yo-sep Min

Sung-Ho Park

Jin-Seok Lee

Kyu-sik Kim

Sung-Wook Hwang

Dong-joon Ma

Choong-Man Lee

Do-Haing Lee

Chan-Jin Park

Ho-kyu Kang

Yoon-dong Park

Moon-Kyung Kim

Soo-Doo Chae

Hyun-sang Hwang

Jong-Duk Lee

Yung-hee Yvette Lee

Chan-jin Park

Jo-Won Lee

A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.

Non-volatile memory device including metal-insulator transition material

A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.

SONOS memory device using an amorphous memory node material

Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Method of erasing a memory device including complementary nonvolatile memory devices

Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

Methods of manufacturing non-volatile memory devices having insulating layers treated using neutral beam irradiation

A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

Method of operating a SONOS memory device

A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

Multi-bit non-volatile memory device, method of operating the same, and method of fabricating the same

Methods of operating and manufacturing logic device and semiconductor device including complementary nonvolatile memory device, and reading circuit for the same

A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

Semiconductor device doped with Sb, Ga, or Bi and method of manufacturing the same

A flash memory device can include a semiconductor fin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor fin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor fin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.

Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same

A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.

Method of fabricating a single electron transistor having memory function

SONOS memory device having nano-sized trap elements

Semiconductor device doped with Sb, Ga or Bi and method of manufacturing the same

A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Semiconductor device including high-k insulating layer and method of manufacturing the same

Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels

A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.

CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor

Growing community of inventors

Suwon-si, South Korea

Chung-woo Kim