Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Chi Mei Optoelectronics Corporation

Au Optronics Corporation

Chunghwa Picture Tubes, Ltd.

Hannstar Display Corporation

Toppoly Optoelectronics Corporation

Quanta Display Inc.

Taiwan Tft Lcd Association

Chung-Wen Wu

Chih-Yuan Ting

Jyu-Horng Shieh

Jeng-Shiou Chen

Shiu-Ko JangJian

Chien-Chung Chen

Chien-Wen Chiu

Jang-Shiang Tsai

Ya-Lien Lee

Hsin-Chun Chiang

Ching-Wen Hsiao

Yu-Yang Chang

Yi-Ping Lin

Yi-An Sha

Jane-Hway Liao

Bang-Hao Wu

Lung-Pin Hsin

Kang-Hung Liu

Yang-Yi Fan

Yi-Chun Wong

Tsan-Yu Ho

Yu-Ming Chen

Ing Jer Lin

A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Interconnect line for semiconductor device

An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Interconnection structure and manufacturing method thereof

One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.

Mitigating pattern collapse

The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

Patterning approach for improved via landing profile

Method and apparatus for back end of line semiconductor device processing

Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.

Method of preventing pattern collapse

Methods of patterning a target material layer are provided herein. The method includes steps of positioning a semiconductor wafer having the target material layer thereon in an etch chamber and of providing a flow of etch gases into the etch chamber, the flow of etch gases etchant gas comprising a plurality of gases. The semiconductor wafer has a patterned hardmask feature formed from a compound on the target material layer. The method also includes steps of etching the target material layer using the patterned hardmask feature as a mask feature, wherein one of the gases chemically alters the patterned hardmask feature and at least one of the gases chemically repairs the patterned hardmask feature so that the patterned hardmask feature retains its dimensions during the etching. Associated semiconductor wafer are also provided herein.

Systems and methods for in SITU maintenance of a thin hardmask during an etch process

A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x, y) of a first conducting feature has a dimension of (x&#x3c;y), a top and bottom width (x, y) of a second conducting feature has a dimension of (x&#x3c;y; x=y; or x&#x3e;y), and a top and bottom width (x, y) of a third conducting feature has a dimension of (x&#x3e;y). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.

Formation method of interconnection structure of semiconductor device

Growing community of inventors

Zhubei, Taiwan

Chung-Wen Wu