Industrial Technology Research Institute

Chung Wen Huang

Chi-Lung Wang

Yi-Ping You

Kuo Yu Chuang

Jeng Kuen Lee

A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Growing community of inventors

Chiayi County, Taiwan

Chung Wen Huang