Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Wei Wu

Zhiqiang Wu

Chun-Fu Cheng

Wen-Hsing Hsieh

Kuan-Lun Cheng

Jon-Hsu Ho

Wei Ju Lee

Chih-Ching Wang

Wen-Yuan Chen

Chung-I Yang

Meng-Yu Lin

Peng-Chun Liou

Li-Jui Chen

Shang-Chieh Chien

Heng-Hsin Liu

Yi-Ching Liu

Tai-Yu Chen

Tzer-Min Shen

Chieh Hsieh

Kuan-Ting Liu

Szu-Wei Huang

Gwan-Sin Chang

Kuo-An Liu

Yen-Tien Tung

Kai Tak Lam

Yin-Chuan Chuang

Sagar Deepak Khivsara

Yung-Chien Huang

Zhi-Ren Xiao

Chia-Ying Su

Ching-Wei Tsai

Meng-Han Lin

Yih Wang

Han-Jong Chia

Yu-Xuan Huang

Shin-Jiun Kuang

Yu-Chien Chiu

Chun-fu Cheng

Wei-Ju Lee

Zhi-Chang Lin

Cheng-Ting Chung

Jin Cai

Ya-Yun Cheng

Chia-En Huang

Zhi-Qiang Wu

Chun Chung Su

Mahaveer Sathaiya Dhanyakumar

Chien-Hong Chen

Chun-Chung Su

A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

Field effect transistor with merged epitaxy backside cut and method

A method includes forming a dielectric layer over a substrate; forming a carbon nanotube (CNT) over the dielectric layer; forming a dummy gate structure over the CNT; forming gate spacers on opposite sidewalls of the dummy gate structure; forming source/drain epitaxy structures on opposite sides of the dummy gate structure and in contact with opposite sidewalls of the CNT; replacing the dummy gate structure with a metal gate structure; and forming source/drain contacts over the source/drain epitaxy structures, respectively.

Semiconductor device and method for forming the same

Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Source/drain silicide for multigate device performance and method of fabricating thereof

A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Effective work function tuning via silicide induced interface dipole modulation for metal gates

A ferroelectric memory device includes a multi-layer stack, a ferroelectric layer, and channel layers. The multi-layer stack is disposed on a substrate and includes conductive layers and dielectric layers stacked alternately. The ferroelectric layer has a curvy profile and is disposed along sidewalls of the conducive layers and sidewalls of the dielectric layers. The channel layers are separated from each other and disposed on the ferroelectric layer, and correspond to the conductive layers respectively.

Ferroelectric memory device and method of forming the same

Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

Gate all around transistor device and fabrication methods thereof

A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.

Semiconductor device and manufacturing method thereof

The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.

Multi-gate devices and fabricating the same with etch rate modulation

A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Semiconductor memory device and manufacturing method thereof

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Source/drain features with improved strain properties

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.

Method of manufacturing a multi-gate device having a semiconductor seed layer embedded in an isolation layer

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Semiconductor memory devices and methods of manufacturing thereof

A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.

System and method for performing extreme ultraviolet photolithography processes

Growing community of inventors

Hsin-Chu County, Taiwan

Chung-Wei Wu