Mosel Vitelic Corporation

Lucent Technologies Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

Promos Technologies, Inc

Chung Wai Leung

Ranbir Singh

Chia-Shun Hsiao

Yih-Feng Chyan

Vei-Han Chan

Yi Ma

Hsing Ti Tuan

Patrick J Kelley

Jin-Ho Kim

Chunchieh Huang

Yue-Song He

Richard Joseph McPartland

Li-Chun Li

Alan Sangone Chen

Ross Alan Kohler

Ching-Hwa Chen

Zhong Dong

Chuck Jang

Joseph Rudolph Radosevich

Barbara Haselden

Shahriar Moinian

Richard William Gregor

Kuei-Chang Tsai

George Kovall

Thomas Tong-Long Chang

Timothy Scott Campbell

William John Nagy

Daniel Mark Wroge

Jane Qian Liu

Dayo Alugbin

Kwok Kwok Ng

Demi Nguyen

Steven Ming Yang

Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

Method of forming ONO-type sidewall with reduced bird's beak

A memory cell () has a plurality of floating gates (L,R). The channel region () comprises a plurality of sub-regions (L,R) adjacent to the respective floating gates, and a connection region () between the floating gates. The connection region has the same conductivity type as the source/drain regions () to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric () becomes thick between the floating gates, weakening the control gate's () electrical field in the channel.

Nonvolatile memory cell with multiple floating gates and a connection region in the channel

To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

Nonvolatile memory structures and fabrication methods

The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

Method of making a bipolar transistor with an oxygen implanted emitter window

Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Dummy structures that protect circuit elements during polishing

The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

Bipolar transistor with a low K material in emitter base spacer regions

In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( ), and also includes conductive spacers ( ). The spacers increase the capacitive coupling between the floating gate and the control gate ( ).

Nonvolatile memories with floating gate spacers, and methods of fabrication

In a nonvolatile memory, a floating gate ( ) is covered with ONO ( ), and a control gate polysilicon layer ( ) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer ( ) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion ( ) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric ( ) is therefore reduced. Other embodiments are also provided.

Sidewall protection in fabrication of integrated circuits

The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

Flash memory device having a bipolar transistor formed integral thereto and a method of manufacture therefor

An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Integrated circuit fabrication

A bipolar device ( ) includes an oxide layer ( ) which is grown on the surface ( ) of a semiconductor substrate ( ) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water

A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 10 to about 10 cm before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

Bipolar semiconductor device and method of forming same having reduced transient enhanced diffusion

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Milpitas, CA, United States of America

Chung Wai Leung