International Business Machines Corporation

Chung W Ho

Dudley A Chance

Christopher H Bajorek

Sudipta Kumar Ray

Timothy C Reiley

David A Thompson

Alan Platt

A chip carrying module includes a number of engineering change lines buried below the surface of the module. The engineering change lines are interrupted periodically to provide a set of vias extending up to the upper surface of the module between each set of chips where the vias are connected by dumbbell-shaped pads including a narrow link which permits laser deletion or the like. In addition, the dumbbell-shaped pads are located adjacent to the fan-out pads for the chips. Thus, the fan-out pads can be connected to the dumbbell-shaped pads by means of fly-wires. In addition, individual engineering change lines can be connected together to reach every region of the module by connecting a fly-wire from one dumbbell-shaped pad to another. In addition, by deleting the links at such dumbbell-shaped pads, the engineering change connections are limited to the particular path required.

Chip carrier with embedded engineering change lines with severable

A laminated capacitor is joined to the surface of a chip carrier for large scale integrated circuit chips. The capacitor lies adjacent to positions where chips are located. The capacitor includes a plurality of capacitor plates. The capacitor is bonded to the chip carrier with an array of solder bars comprising an elongated strip of metallic material. Each of the bars is connected to a set of the capacitor plates in the laminated capacitor by means of tab connections on the plates, whereby each of the plates is connected by a plurality of tabs to a plurality of the solder bars. Methods of fabrication of the laminated capacitor structure and solder bars are described.

Low inductance MLC capacitor with metal impregnation and solder bar

A chip carrier system for supporting electronic semiconductor chips is provided with a matched coefficient of thermal expansion as well as a high value of capacitance. The carrier provides both mechanical and electrical connections to the chip. A small sized interposer for a silicon chip possesses high capacitance. An array of dot capacitors is formed between laminated layers of ceramic material. In some cases, conductive surfaces are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets.

Capacitive chip carrier and multilayer ceramic capacitors

A module carrying microcircuit LSI chips includes stacks of parallel ceramic sheets carrying thin capacitor plates laminated in a ceramic structure in which the capacitor plates either serve (1) as the power distribution conductors known as power planes or (2) are connected to power conducting vias which pass through the capacitor plates. Those vias connect to the appropriate capacitor plates electrically, thereby locating the capacitance required as close as possible to the solder bonds between the chips and the carrier. Stacks of laminated ceramic capacitors serving as power planes can be inserted into slots in laminated ceramic sheets providing the first arrangement above. Signal vias are provided about the periphery of the power planes. A highly parallel distribution of current is provided by means of horizontal power conducting straps which reduce voltage fluctuations, electrical resistance, and current per via.

Multiple layer, ceramic carrier for high switching speed VLSI chips

A module for LSI chips includes an orthogonal array of sets of pads and fan-out metallization for a large number of chips. Running parallel to the sides of the chips and the fan-out area are several parallel prefabricated, thin film engineering change interconnection lines terminating in pads adjacent to the fan-out. The pads are arranged to permit discretionary connections of the fan-out pads to the engineering change pads with minimal crossovers by means of short fly wires. A staggered pad arrangement minimizes potential crossovers and maximizes the number of interconnection lines that can be fabricated.

Discretionary fly wire chip interconnection

Microcircuit chip packages mounted modules are connected together by lossy strip transmission lines parallel to a ground plane without termination. The transmission line segments are designed to have a total resistance R.sub.L which is within the range between two-thirds and two times the characteristic impedance Z.sub.o of the transmission line. Reflections are prevented from causing signal problems by maintaining R.sub.L above the minimum value. Similarly, the maximum value is intended to prevent deterioration of the wave shape.

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Chappaqua, NY, United States of America

Chung W Ho