Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Ting Lu

Chung-Chieh Yang

Chih-Chiang Chang

Yung-Chow Peng

Chung-Peng Hsieh

Tai-Yi Chen

Yung-Shun Chen

Chih-chiang Chang

Nai Chen Cheng

Yang Chung-Chieh

Chin-Hua Wen

A device includes an electrical circuit. The device further includes a first conductive pillar over a first side of a substrate. The device further includes a first conductive rail electrically connected to the first conductive pillar, wherein the electrical circuit is electrically connected to the first conductive rail by the first conductive pillar. The device further includes a power pillar extending through the substrate, wherein the power pillar is electrically connected to the first conductive rail.

Power cell for semiconductor devices

A semiconductor device includes a metal-oxide-metal (MOM) cell including a first bus at a first elevation and extending along a first direction, and a second bus at a second elevation, extending along a second direction different from the first direction, and electrically connected to the first bus through a via. The MOM cell also includes a first group of fingers at the first elevation and extending along the first direction; and a second group of fingers at the second elevation and extending along the second direction. Each finger of the first group of fingers is electrically connected to the second bus through a corresponding via, each finger of the second group of fingers is electrically connected to the first bus through a corresponding via, and each finger of the first group of fingers overlaps each finger of the second group of fingers.

Metal-oxide-metal cell semiconductor device and method

A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage.

Middle end of line decoupling capacitors for semiconductor devices and methods of manufacturing thereof

An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

Analog cells utilizing complementary mosfet pairs

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Two-step charge-based capacitor measurement

The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Circuitry and method for reducing environmental noise

A device includes an electrical circuit having a first set of circuit elements. The device further includes a first set of conductive pillars over a first side of a substrate. The device further includes a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail. The device further includes a first plurality of power pillars extending through the substrate, wherein each of the first plurality of power pillars is electrically connected to the first conductive rail.

Semiconductor devices including decoupling capacitors and methods of manufacturing thereof

A semiconductor device includes an electrical circuit having a first set of circuit elements, wherein the electrical circuit is in a circuit area on a first side of a substrate, and a first set of conductive pillars over the first side of the substrate. In the semiconductor device, a first conductive rail electrically connects to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail; and a first power cell extending through the substrate, wherein the first power cell includes a first number of power pillars extending through the substrate, wherein each of the first number of power pillars electrically connects to the first conductive rail in parallel.

Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example.

Array modeling for one or more analog devices

Among other things, one or more systems and techniques for transition time evaluation of a circuit are provided herein. In some embodiments, a comparator is configured to receive a circuit signal from the circuit. The circuit signal is evaluated by the comparator based upon one or more control voltages to create one or more voltage waveforms. In some embodiments, the one or more voltage waveforms have substantially similar slopes. A time converter, such as a time-to-current converter or a time-to-digital converter, is used to evaluate the one or more output waveforms to determine a transition time, such as a rise time or a fall time, of the circuit. In some embodiments, the one or more output waveforms are used to reconstruct a transition waveform representing a waveform of the circuit signal.

Rise time and fall time measurement

A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier.

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Kaohsiung, Taiwan

Chung-Ting Lu