Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Te Lin

Sheng-Chih Lai

Katherine H Chiang

Feng-Cheng Yang

Hai-Ching Chen

Han-Ting Tsai

Yu-Ming Lin

Ting-Wei Chiang

Hui-Zhong Zhuang

Li-Chun Tien

Han-Jong Chia

Tai-Yen Peng

Hui-Hsien Wei

Meng-Han Lin

Sheng-Chen Wang

Mauricio Manfrini

Wei-Chih Wen

Pin-Cheng Hsu

Chien-Min Lee

Yen-Chung Ho

Yen-Chieh Huang

Tung-Heng Hsieh

Yu-Wei Jiang

Pin-Dai Sue

Pin-Ren Dai

Sheng-Hsiung Wang

Sai-Hooi Yeong

Lee-Chung Lu

Min Cao

Kuo-Chang Chiang

Chia-Jung Yu

Sheng-Hsiung Chen

Cheng-Yi Wu

Yu-Feng Yin

Gerben Doornbos

Po-Hsiang Huang

Chien-Hua Huang

Chun-Chen Chen

Jyu-Horng Shieh

Bo-Feng Young

Fong-yuan Chang

Ru-Shang Hsiao

Hung-Chang Sun

Tsann Lin

Mark Van Dal

Jung-Chan Yang

Randy B Osborne

Ken-Ichi Goto

Fong-Yuan Chang

An-Shen Chang

Chin-Chou Liu

Chih-Yu Chang

Yi-Ching Liu

Jerry Chang Jui Kao

Yen-Sen Wang

Yen-Ming Chen

Wei-Yang Lee

Shou-Gwo Wuu

Kuo-Hua Pan

Marcus Johannes Henricus Van Dal

Chien-Hsien Tseng

Wei-Yuan Lu

TsuChing Yang

Han-Ting Lin

Ho Che Yu

Ru-Gun Liu

Chung-Ju Lee

Tzu-Chiang Chen

Shih-Ming Chang

Hung-Li Chiang

Tsai-Sheng Gau

Shy-Jay Lin

Ming-Feng Shieh

Chih-Yuan Ting

Chun-Chieh Lu

Wei-Hao Liao

Hsi-Wen Tien

Chih-Wei Lu

Feng-Ching Chu

Gwan Sin Chang

Min-Hsiung Chiang

Yu-Teng Dai

Li-Shyue Lai

Chia-en Huang

Yu-Shu Chen

Kong-Beng Thei

Chi-Hsi Wu

Chia-En Huang

Mariam G Sadaka

Kuang-Hsin Chen

Kai-Wen Cheng

Tzer-Min Shen

Ting Yu Chen

Cheng-Hung Chang

Wei Chuang Wu

Tsung-Chieh Tsai

Su-Yu Yeh

Hsien-Chin Lin

Ying-Chih Chen

Ya-Yun Cheng

A semiconductor device includes a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed over the substrate. The gate dielectric layer is disposed over the gate electrode. The channel layer is disposed over the gate dielectric layer. The source electrode and the drain electrode are disposed over the channel layer and beside the gate electrode. In some embodiments, each of the source electrode and the drain electrode includes a glue layer and a metal pattern, and a thickness of the glue layer adjacent to a sidewall of the metal pattern is greater than a thickness of the glue layer adjacent to a bottom of the metal pattern.

Thin film transistor featuring variable thickness glue layer with tapered end

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.

Thin film transistor including a compositionally-modulated active region and methods for forming the same

Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Bipolar selector with independently tunable threshold voltages

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Memory device and method for fabricating the same

Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Ferroelectric memory device and method of forming the same

A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Memory cell having source or drain electrode with kink portion, memory array and manufacturing method thereof

A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

Three-dimensional memory device with word lines extending through sub-arrays, semiconductor device including the same and method for manufacturing the same

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

Access transistors in a dual gate line configuration and methods for forming the same

In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.

3D lateral patterning via selective deposition for ferroelectric devices

An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Ferroelectric memory device with a metal layer having a crystal orientation for improving ferroelectric polarization and method for forming the ferroelectric memory device

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Semiconductor structure and method for forming thereof

A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Semiconductor device

In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

High selectivity isolation structure for improving effectiveness of 3D memory fabrication

A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.

Memory device including a semiconducting metal oxide fin transistor and methods of forming the same

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Tainan, Taiwan

Chung-Te Lin