Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Te Lin

Sheng-Chih Lai

Feng-Cheng Yang

Katherine H Chiang

Han-Ting Tsai

Hai-Ching Chen

Yu-Ming Lin

Ting-Wei Chiang

Hui-Zhong Zhuang

Li-Chun Tien

Han-Jong Chia

Tai-Yen Peng

Hui-Hsien Wei

Meng-Han Lin

Sheng-Chen Wang

Mauricio Manfrini

Wei-Chih Wen

Pin-Cheng Hsu

Chien-Min Lee

Yu-Wei Jiang

Yen-Chung Ho

Tung-Heng Hsieh

Pin-Ren Dai

Yen-Chieh Huang

Sheng-Hsiung Wang

Pin-Dai Sue

Kuo-Chang Chiang

Sai-Hooi Yeong

Lee-Chung Lu

Min Cao

Cheng-Yi Wu

Chia-Jung Yu

Sheng-Hsiung Chen

Yu-Feng Yin

Gerben Doornbos

Po-Hsiang Huang

Chien-Hua Huang

Chun-Chen Chen

Jyu-Horng Shieh

Hung-Chang Sun

Tsann Lin

Bo-Feng Young

Fong-yuan Chang

Ru-Shang Hsiao

Mark Van Dal

Jung-Chan Yang

Randy B Osborne

Ken-Ichi Goto

Fong-Yuan Chang

An-Shen Chang

Yen-Ming Chen

Wei-Yang Lee

Chin-Chou Liu

Chih-Yu Chang

Yi-Ching Liu

Jerry Chang Jui Kao

TsuChing Yang

Yen-Sen Wang

Shou-Gwo Wuu

Kuo-Hua Pan

Marcus Johannes Henricus Van Dal

Chien-Hsien Tseng

Wei-Yuan Lu

Feng-Ching Chu

Han-Ting Lin

Ho Che Yu

Ru-Gun Liu

Chung-Ju Lee

Tzu-Chiang Chen

Shih-Ming Chang

Hung-Li Chiang

Shy-Jay Lin

Tsai-Sheng Gau

Ming-Feng Shieh

Chih-Yuan Ting

Chun-Chieh Lu

Wei-Hao Liao

Hsi-Wen Tien

Chih-Wei Lu

Chia-en Huang

Gwan Sin Chang

Min-Hsiung Chiang

Yu-Teng Dai

Li-Shyue Lai

Yu-Shu Chen

Kong-Beng Thei

Chi-Hsi Wu

Chia-En Huang

Mariam G Sadaka

Kuang-Hsin Chen

Kai-Wen Cheng

Tzer-Min Shen

Ting Yu Chen

Cheng-Hung Chang

Wei Chuang Wu

Tsung-Chieh Tsai

Su-Yu Yeh

Hsien-Chin Lin

Ying-Chih Chen

Ya-Yun Cheng

A transistor includes a gate electrode, a gate dielectric, a channel layer and a source line and bit line. The gate electrode includes a first gate material layer and a second gate material layer disposed on the first gate material layer, wherein a work function of the first gate material layer is lower than a work function of the second gate material layer. The gate dielectric is disposed on the gate electrode. The channel layer is disposed on the gate dielectric. The source line and bit line are disposed on and connected to the channel layer.

Integrated circuit, transistor and method of fabricating the same

A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer and memory material layer penetrate through the plurality of conductive layers and the plurality of dielectric layers. The at least three conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive layers respectively. The at least three conductive pillars includes a first, a second and a third conductive pillars disposed between the first conductive pillar and the second conductive pillar. A third width of the third conductive pillar is smaller than a first width of the first conductive pillar and a second width of the second conductive pillar.

Memory device and method of forming the same

A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

A semiconductor memory device is provided. The semiconductor memory device includes a first access line extending in a horizontal direction, a first column of memory cells over the first access line, a second column of memory cells adjacent to the first column of memory cells, and a second access line over the first column of memory cells and the second column of memory cells and extending in the horizontal direction. The first column of memory cells includes a first gate line electrically connected to the first access line, and the second column of memory cells includes a second gate line electrically connected to the second access line.

Semiconductor memory device with vertical gate line

A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

Three-dimensional memory device and method

Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ≤3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ≥7 nm). Ferroelectric layers having larger mean grain sizes may exhibit enhanced crystallinity and a stabilized orthorhombic crystal phase, particularly in relatively thin layers (e.g., ≤15 nm in thickness).

Ferroelectric memory devices having improved ferroelectric properties and methods of making the same

A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.

High-density 3D-DRAM cell with scaled capacitors

A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Semiconductor device with air-spacer

In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Three-dimensional memory devices

Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Transistor structure and method of forming the same

A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Transistor including a hydrogen-diffusion barrier and methods for forming the same

An integrated circuit includes a first gate electrode structure extending in a first direction. The integrated circuit includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Integrated circuit having angled conductive feature

A semiconductor device includes a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed over the substrate. The gate dielectric layer is disposed over the gate electrode. The channel layer is disposed over the gate dielectric layer. The source electrode and the drain electrode are disposed over the channel layer and beside the gate electrode. In some embodiments, each of the source electrode and the drain electrode includes a glue layer and a metal pattern, and a thickness of the glue layer adjacent to a sidewall of the metal pattern is greater than a thickness of the glue layer adjacent to a bottom of the metal pattern.

Thin film transistor featuring variable thickness glue layer with tapered end

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.

Thin film transistor including a compositionally-modulated active region and methods for forming the same

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Tainan, Taiwan

Chung-Te Lin