Industrial Technology Research Institute

Chung-Tao Chang

Chia-Chung Wang

Hsin-Chien Huang

Hsiu-Tsang Lee

Enboa Wu

Jane Huei-Chen Chang

Chien Sheng Chen

Kuo-Chuan Chen

Tsung-Yao Chu

Chih-Hsiang Ko

Steven Jyh-Ren Yang

Steven J Yang

Jyh-Ren Yang

Bi-Chu Wu

Jane Huei-Chen Chan

Ruey-Wen Chien

An optoelectronic transceiver that has integrated optical and electronic components, and can be passively aligned by a flip-chip method and a mechanical method is provided. The optoelectronic transceiver can be constructed by the key components of a circuit board, a silicon sub-mount, at least two IC chips formed on a silicon sub-mount, a microlens array, an optical fiber, and a receptacle for housing the silicon sub-mount, the at least two IC chips, the microlens array and the optical fiber connector in an aligned configuration. The at least two IC chips preferably include a laser diode, a laser diode driver, a photodetector and a photodetector amplifier. The mechanical alignment between a microlens array and a silicon sub-mount is performed by indentations provided in the surfaces of the two parts and the placement of spacer balls in the indentations.

Optoelectronic transceiver having integrated optical and electronic components

A method for forming solder bumps for a flip-chip bonding process wherein the bumps have substantially the same height and structures formed by the method are described. In the method, a pre-processed semiconductor substrate that has a plurality of metal traces formed on a top surface is first provided. At least two solder non-wettable masking strips are then deposited on top of and perpendicular to the plurality of metal traces. The at least two solder non-wettable masking strips are deposited spaced-apart at a predetermined spacing sufficient for forming a bond pad therein-between on the plurality of metal traces. Finally, a solder material is deposited onto the bond pads forming solder bumps which are then reflown into solder balls.

Method for forming solder bumps for flip-chip bonding by using perpendicularly laid masking strips

A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.

Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication

Automatic alignment methods for a membrane prober are disclosed. Alignment patterns are designed and manufactured on both a membrane prober and a wafer under test. The patterns are properly designed for acquiring a first set of measurement data that provide relative position information when the prober contacts the wafer. A second set of measurement data can be obtained by a controlled move between the prober and the wafer. The relative position including the translation offset and the rotation angle can be computed by the information derived from the two sets of measurement data. The second set of measurement data may also be acquired by having two alignment pattern pairs that are made to contact in a single touch. More accurate aligrnent can be achieved by using more pairs of alignment patterns.

Contact type prober automatic alignment

An IC die formed with built-in stress test pattern and a method for forming such pattern are described. The stress test pattern may be formed by first forming a thermal oxide insulation layer on a silicon substrate, then forming a first plurality of diagonally positioned linear metal traces of a first metal, then depositing an electrically insulating material layer on top of the first plurality of diagonally positioned metal traces, and forming a second plurality of L-shaped metal bars of a second metal positioned with the two sides of L parallel to the two sides of a corner region and overlapping the first plurality of metal traces with the electrically insulating material layer therein between. The double metal method for forming the stress test pattern can be easily incorporated into the fabrication process for an IC die without any additional deposition or photolithographic steps. The metal,and metal,layers may be suitably formed of aluminum or an aluminum alloy, or any other conductive metallic material. The L-shaped metal bars formed by the metal,layer should intersect the linear metal traces at a 45&deg; angle with an isolation layer therein between. An electrical resistance between the two metal layers can be determined by a leakage current therein between as a direct indication of the thermo-mechanical stresses, or shear stresses existing between the two metal layers. The present invention stress test pattern can be formed in any size or dimensions as long as one metal layer is formed in linear, diagonal strips while the other metal layer is formed in L-shaped metal bars overlapping the first metal layer.

Built-in stress pattern on IC dies and method of forming

Automatic alignment methods for a membrane prober are disclosed. Alignment patterns are designed and manufactured on both a membrane prober and a wafer under test. The patterns are properly designed for acquiring a first set of measurement data that provide relative position information when the prober contacts the wafer. A second set of measurement data can be obtained by a controlled move between the prober and the wafer. The relative position including the translation offset and the rotation angle can be computed by the information derived from the two sets of measurement data. The second set of measurement data may also be acquired by having two alignment pattern pairs that are made to contact in a single touch. More accurate alignment can be achieved by using more pairs of alignment patterns.

A switchable I/O buffer for multi-chip modules comprising a conventional I/O buffer and a miniaturized I/O buffer. A path switch selects the conventional I/O buffer or the minaturized I/O buffer according to whether the I/O interconnection is for communication off the module or chip-to-chip communication within the module. The miniaturized I/O buffer comprises a single-ended I/O buffer without electrostatic discharge protection. Two layout structures are designed for the switchable I/O buffer. A first layout structure having its path switching control provided by either a cell-programmable method or a mask-programmable method can be used for a multi-chip module or a PWB single package. A second layout structure using a pad-programmable method to provide the path switching control is suitable for a multi-chip module with flip-chip attachment technology. Four different circuit implementations of the switchable I/O buffer are presented. The switchable I/O buffer achieves higher performance with lower power dissipation in that the unnecessary heavy loading and electrostatic discharge protection are eliminated from the interconnection for chip-to-chip communication within the multi-chip module.

Growing community of inventors

Hsinchu, Taiwan

Chung-Tao Chang