Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Other

Chung-Shi Liu

Chen-Hua Douglas Yu

Ming-Da Cheng

Chih-Wei Lin

Hao-Yi Tsai

Wei-Hung Lin

Hsiu-Jen Lin

Meng-Tse Chen

Hung-Jui Kuo

Wei-Yu Chen

Chien Ling Hwang

Ching-Hua Hsieh

Kuei-Wei Huang

Wen-Hsiung Lu

Tin-Hao Kuo

Mirng-Ji Lii

Ming-Che Ho

Hui-Min Huang

Jiun Yi Wu

Chien-Hsun Lee

Yi-Wen Wu

Yu-Hsiang Hu

Chun-Cheng Lin

Cheng-Ting Chen

Bor-Ping Jang

Hung-Yi Kuo

Chih-Fan Huang

Chih-Hua Chen

Yu-Feng Chen

Yu-Chih Huang

Yu-Chia Lai

Shau-Lin Shue

Cheng-Chieh Hsieh

Hsien-Wei Chen

Tsung-Yuan Yu

Chih-Hsuan Tai

Yeong-Jyh Lin

Jiun-Yi Wu

Chao-Wen Shih

Chen-Shien Chen

Tsung-Ding Wang

Yi-Li Hsiao

Ming Hung Tseng

Shou-Zen Chang

Hui-Jung Tsai

Syun-Ming Jang Jang

Han-Ping Pu

Alexander Kalnitsky

Sih-Hao Liao

Chin-Yu Ku

Chien-Hsiun Lee

Chewn-Pu Jou

Chuei-Tang Wang

Shih-Wei Liang

Kuo-Chio Liu

Kai-Chiang Wu

Chen-Cheng Kuo

Yu-Min Liang

Ching-Wen Hsiao

Chun-Chieh Wang

Yen-Liang Lin

Hsin-Yu Pan

Tsung-Hsien Chiang

Chi-Ming Tsai

Shin-Puu Jeng

Wen-Chih Chiou

Der-Chyang Yeh

Tien-I Bao

Kong-Beng Thei

An-Jhih Su

Chun-Hung Lin

Chih-Hang Tung

Wei-Chih Chen

Ching-Jung Yang

Sheng-Yu Wu

Ming-Kai Liu

Shien-Yang Wu

Harry-Hak-Lay Chuang

Mong-Song Liang

Kuo-Chung Yee

Ying-Lang Wang

Chih-Hao Chang

Li-Hsien Huang

Chung-Hao Tsai

Feng-Wei Kuo

Cheng-Tung Lin

Chung-Long Chang

Chih-Cheng Lin

Jung Wei Cheng

Chia-Shiung Tsai

Ming-Fa Chen

Horng-Huei Tseng

Mei-Yun Wang

Sung-Feng Yeh

Keng-Chu Lin

Cheng-Lin Huang

Weng Chang

Harry Chuang

Hsien-Ming Lee

Wei-Ting Lin

A semiconductor package includes a first integrated circuit, a first conductive via, a second conductive via, a second integrated circuit, a third conductive via and an encapsulant. The first conductive via is disposed in a first passivation layer over the first integrated circuit. The second conductive via is disposed in a second passivation layer over the first passivation layer. The second conductive via is electrically connected to the first conductive via. The third conductive via is disposed over the second integrated circuit, wherein a surface of the third conductive via is substantially coplanar with a surface of the third conductive via. The encapsulant encapsulates the first integrated circuit, the first passivation layer, the second passivation layer, the second integrated circuit and the third conductive via.

Semiconductor packages and method of manufacturing the same

A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

Methods of manufacturing integrated fan-out packages with embedded heat dissipation structure

A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

Semiconductor package and method

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

Method for manufacturing semiconductor package with connection structures including via groups

A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Warpage control of packages using embedded core frame

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

3D integrated circuit (3DIC) structure

In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

Integrated circuit package and method

A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same

An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Stacked memory cube with integrated thermal path for enhanced heat dissipation

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

Semiconductor package and manufacturing method thereof

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Hsinchu, Taiwan

Chung-Shi Liu