Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Other

Chung-Shi Liu

Chen-Hua Douglas Yu

Ming-Da Cheng

Chih-Wei Lin

Hao-Yi Tsai

Wei-Hung Lin

Hsiu-Jen Lin

Meng-Tse Chen

Hung-Jui Kuo

Wei-Yu Chen

Chien Ling Hwang

Ching-Hua Hsieh

Kuei-Wei Huang

Wen-Hsiung Lu

Tin-Hao Kuo

Mirng-Ji Lii

Ming-Che Ho

Hui-Min Huang

Yi-Wen Wu

Yu-Hsiang Hu

Jiun Yi Wu

Chien-Hsun Lee

Chun-Cheng Lin

Cheng-Ting Chen

Bor-Ping Jang

Hung-Yi Kuo

Chih-Fan Huang

Chih-Hua Chen

Yu-Feng Chen

Yu-Chih Huang

Yu-Chia Lai

Shau-Lin Shue

Cheng-Chieh Hsieh

Hsien-Wei Chen

Tsung-Yuan Yu

Yeong-Jyh Lin

Chih-Hsuan Tai

Jiun-Yi Wu

Chao-Wen Shih

Kuo Lung Pan

Chen-Shien Chen

Tsung-Ding Wang

Yi-Li Hsiao

Ming Hung Tseng

Shou-Zen Chang

Hui-Jung Tsai

Syun-Ming Jang Jang

Han-Ping Pu

Alexander Kalnitsky

Sih-Hao Liao

Chin-Yu Ku

Chien-Hsiun Lee

Chewn-Pu Jou

Chuei-Tang Wang

Shih-Wei Liang

Kuo-Chio Liu

Kai-Chiang Wu

Chen-Cheng Kuo

Yu-Min Liang

Ching-Wen Hsiao

Chun-Chieh Wang

Yen-Liang Lin

Hsin-Yu Pan

Tsung-Hsien Chiang

Chi-Ming Tsai

Shin-Puu Jeng

Der-Chyang Yeh

Tien-I Bao

Kong-Beng Thei

An-Jhih Su

Chun-Hung Lin

Chih-Hang Tung

Wei-Chih Chen

Ching-Jung Yang

Sheng-Yu Wu

Ming-Kai Liu

Shien-Yang Wu

Wen-Chih Chiou

Harry-Hak-Lay Chuang

Mong-Song Liang

Kuo-Chung Yee

Ying-Lang Wang

Chih-Hao Chang

Li-Hsien Huang

Chung-Hao Tsai

Feng-Wei Kuo

Cheng-Tung Lin

Chung-Long Chang

Jung Wei Cheng

Chih-Cheng Lin

Chia-Shiung Tsai

Ming-Fa Chen

Horng-Huei Tseng

Mei-Yun Wang

Sung-Feng Yeh

Keng-Chu Lin

Cheng-Lin Huang

Harry Chuang

Weng Chang

Hsien-Ming Lee

In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

Integrated circuit package and method

A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same

An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Stacked memory cube with integrated thermal path for enhanced heat dissipation

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

Semiconductor package and method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern. The conductive vias extend through the molded semiconductor device and are electrically connected with the redistribution pattern.

Semiconductor package and manufacturing method thereof

A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

IPD modules with flexible connection scheme in packaging

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Methods of forming semiconductor packages

A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.

Molded semiconductor device and manufacturing method of molded semiconductor device

A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

An electronic assembly includes a first wafer including a stack of alternating first dielectric layers and first circuit layers, a flexible structure including a second dielectric layer and a second circuit layer covered by the second dielectric layer, and a second wafer stacked upon the first wafer and including chip packages arranged in an array. The flexible structure includes a first region embedded in the first wafer and a second region connected to the first region and extending out from an edge of the first wafer. The chip packages are electrically coupled to the second circuit layer of the flexible structure through the first circuit layers of the first wafer.

Electronic assembly having circuit carrier

In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Semiconductor device and method of manufacture

Growing community of inventors

Hsinchu, Taiwan

Chung-Shi Liu