Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Chung San Roger Chan

Gary Franklin Chard

T-Pinn Koh

Adam Rappoport

Bennett Lau

Robert Floyd Payne

Frank Vanselow

Nghia Trong Tang

John Mitchell Perry

Richard Mark Prentice

Woo Jin Kim

Samuel M Palermo

Ari Arie Levy

In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.

Clock sync input dropout protection

Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.

Methods and apparatus to transition devices between operational states

Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.

Methods and apparatus to provide clock resynchronization in communication networks

An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop filter for generating a multiple bit digital control signal for the digitally controlled oscillator, a sigma-delta modulator for generating an additional 1-bit digital control signal for the digitally controlled oscillator, a digital divider dividing the oscillator output signal and providing a digital divided signal, and a digital adder with a first, additive input to which the digital reference input is applied and a second, subtractive input to which the digital divided signal is applied. The digital adder provides a digital output, the most significant bits of which are applied to an input of the digital loop filter and the least significant bits of which are applied to an input of the sigma-delta modulator. In the preferred embodiment, the sigma-delta modulator is of a two-stage MASH configuration.

All-digital phase locked loop (ADPLL) system

A differential driver includes two feedback loops and and two inverter pairs and The two feedback loops and regulate the source voltages for the two inverter pairs and to the reference voltages V and V . The two inverter pairs and switch the output load R and C between the two regulated voltages in response to the input voltages IN&plus; and IN&minus;. The reference voltages V and V are created by a reference cell and set the output high and low voltages.

High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization

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Coppell, TX, United States of America

Chung San Roger Chan