Industrial Technology Research Institute

Faraday Technology Corporation

Other

National Yang Ming Chiao Tung University

Chung-Ping Chung

Hui-Chin Yang

Shun-Chieh Chang

Guan-Ying Chiou

Chih-Wei Hsu

Yi-Chi Chen

Shaw-Hwa Hwang

Lung-Chung Chang

Yeu-Horng Shiau

Jin-Chin Chung

Yen-Yuan Chiang

Tzu-Min Chou

Tsung-Hsi Weng

Wei-Hau Chiao

Hsiao-Ping Tsai

Yuan-Jung Kuo

Min-Fu Kao

Lee-Ren Ton

A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.

Dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof

A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.

Processor and method for executing load operation thereof

A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.

Processor and method for recovering global history shift register and return address stack thereof by determining a removal range of a branch recovery table

A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus.

Method and apparatus for bus encoding and decoding

The present invention provides a stack machine for executing a plurality of instructions one by one. The stack machine comprises an operation folder and an execution unit. The operation folder is used for checking if one or more instructions of a predetermined number of instructions following a specific instruction in a predetermined sequence can be folded with the specific instruction according to a POC folding rule. If they are foldable, these instructions will be combined to form a new instruction. The execution unit is used for executing instructions which cannot be folded by the operation folder or new instructions generated by the operation folder one by one. The instructions are folded to enhance operation efficiency of the stack machine.

Method and apparatus for folding a plurality of instructions

A system for converting a hyper text markup language (HTML) document to speech includes an HTML parser, an HTML to speech (HTS) control parser, a tag converter, a text normalizer and a TTS converter. The HTML parser receives data of an HTML formatted document and parses out content text, HTML text tags that structure the content text and control rules used only for translating the received data into sound. The HTS control parser parses control rules for converting the received data into sound. The HTS control parser modifies entries in one or more of a tag mapping table, an audio data table, a parameter set table, an enunciation modification table and a terminology translation table depending on each of the parsed control rules. The text normalizer modifies enunciation of each text string of the content text of the HTML document for which the enunciation modification table has an entry, according to an enunciation modification indicated in the respective enunciation table entry. The text normalizer also translates each text string of the content text of the HTML document for which the terminology translation table has an entry, according to a translation indicated in the respective terminology translation table entry. The tag converter modifies an intonation and a speed of audio generated from the content text of the HTML document encapsulated by each text tag for which the tag mapping table has an entry, as specified in corresponding entries of the parameter set table pointed to by pointers in the tag mapping table. The tag converter also inserts audio for each text tag for which the tag mapping table has an entry, as specified in corresponding entries of the audio data table pointed to by entries of the tag mapping table. The TTS converter converts the content text of the HTML document, as modified, translated and appended by the text normalizer and the tag converter, to speech audio.

Hyper text mark up language document to speech converter

A virtual internet protocol (IP) gate, between a legitimate internet and a virtual internet, can reuse the internet address in a specific range of the legitimate internet addresses for resolving the insufficiency of IP addressing. The virtual IP gate at least comprises a connection module, a selection module and an address conversion module. The connection module establishes connection with the virtual internet by using at least a virtual internet address and establishes connection with the internet by using at least an internet address with the address not within the aforementioned range. The selection module corresponds to a selection port number and receives a transmission packet from a processing module on the legitimate internet to the virtual internet when establishing the connection (including connection-oriented connection and connectionless connection), wherein the &lt;source address: source port number&gt; and &lt;destination address: destination port number&gt; of the delivery packet are the &lt;processing internet address: processing port number&gt; of the processing module and the &lt;internet address of virtual IP gate: the selection port number&gt; of the selection module. Besides, the selection module, in response to a source console, notifies the destination console on the virtual internet of all console names, and transmits the delivery packet to the destination console according to a console selection signal provided by the processing. And an address conversion module is used for converting the addresses between the legitimate internet and the virtual internet.

Virtual internet protocol gate and the network constructed with the same

Growing community of inventors

Hsinchu, Taiwan

Chung-Ping Chung