Ubiquiti Inc.

Alpha Networks Inc.

Chung-Ming Lo

Robert J Pera

Jude Lee

Huan T Vu

Anton N Obukhov

One embodiment of the present invention provides a cloud-based video monitoring system comprising a camera and a network video recorder (NVR). During operation, the camera stores in a buffer last predetermined temporal segment of a video. The camera also stores a first video file in a local storage corresponding to an event detected by the camera. This first video file is non-overlapping with a second video file corresponding to the event and this second video file is stored in the NVR. The camera generates a third video file by pre-pending last predetermined temporal segment of a video prior to the event to the first video file and sends the third video file to the NVR.

Cloud-based video monitoring

A monitoring camera and an operation method thereof are provided. The monitoring camera includes a light sensor, a voltage comparing unit and a reference voltage generating unit. The light sensor senses an environment brightness of the monitoring camera and generates an induced current accordingly. The voltage comparing unit generates a sensing voltage according to the induced current and compares the sensing voltage and a reference voltage to obtain a first comparison result, so that the monitoring camera can determine whether to perform at least one of a plurality of mode switching operations according to the first comparison result. The reference voltage generating unit outputs the first reference voltage and determines whether to reduce the first reference voltage according to the first comparison result.

Monitoring camera and operation method thereof

An interface converting circuit applied between a 3D de-interlace chip and a rear-end image compression chip. The interface converting circuit includes: a reducing FPS circuit, for dividing a first vertical synchronization signal to generate a second vertical synchronization signal, and converting a first horizontal synchronization signal to a second horizontal synchronization signal by masking the first horizontal synchronization signal according to the second vertical synchronization signal; a pixel clock multiplier, for multiplying a first pixel clock signal to generate a second pixel clock signal; and, a data-width converter, for converting an input signal with M bits data width, which is transmitted at a frequency of the first pixel clock signal by the 3D de-interlace chip, to an output signal with M/2 bits data width, which is transmitted at a frequency of the second pixel clock signal.

Growing community of inventors

Hsinchu, Taiwan

Chung-Ming Lo