The Hong Kong Polytechnic University

Chung Ming Lau

Wai Man Tam

Chi Kong Tse

Cheuk Chi Albert Ng

Zhongping Yao

Chiu-Wing Sham

Chiu Wing Sham

Xu Chen

Yue Zhao

Jianfeng Fan

Wal Man Tam

Qing Lu

Methods and systems for storing digital data into peptide sequences and retrieving digital data from peptide sequences are disclosed. The method for storing digital data into peptide sequences may include: encoding the digital data into a digital code; translating the digital code into the peptide sequences; and synthesizing the translated peptide sequences. The method for retrieving digital data from peptide sequences may include: sequencing and determining an order of the peptide sequences; converting the peptide sequences with the determined order into a digital code; and decoding the digital data from the digital code. Codes with error-correction capability are developed for encoding digital data into peptide sequences, and a computational method implemented in a software is developed for sequencing the digital data bearing peptides.

Data storage using peptides

This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages. The sub-decoders are configured to operate concurrently for simultaneously decoding individual sub-codes.

Decoder architecture for cyclically-coupled quasi-cyclic low-density parity-check codes

A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder () for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors () to receive channel messages and edge-messages; each processor () having: a plurality of block processing units (BPUs) (), each BPU () having a plurality of check node processors (CNPs) () to process check nodes that enter into the processor () and a plurality of variable node processors (VNPs) () to process variable nodes that are about to leave the processor (); and a plurality of Random Access Memory (RAM) blocks () for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (), the VNPs () are directly connected to corresponding RAM blocks (), and the CNPs () are directly connected to corresponding RAM blocks () such that the connections from the VNPs () and CNPs () to the corresponding RAM blocks () are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.

High throughput decoder architecture for low-density parity-check convolutional codes

An approximated lower-triangle structure for the parity-check matrix of low-density parity-check (LDPC) codes which allows linear-time-encoding complexity of the codes is disclosed, and the parity part of the parity-check matrix is semi-deterministic which allows high flexibility when designing the LDPC codes in order to provide higher error-correction capabilities than a typical dual-diagonal structure.

Method and system for encoding and decoding low-density-parity-check (LDPC) codes

Growing community of inventors

Hong Kong, China

Chung Ming Lau