Himax Technologies, Inc.

Ncku Research and Development Foundation

Institute for Information Industry

Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

Himax Media Solutions, Inc.

Lncku Research and Development Foundation

Chung-Ming Huang

Soon-Jyh Chang

Yen-Long Lee

Lin-Kai Bu

Chih-Haur Huang

Guan-Ying Huang

Shih-Yang Lin

Chung-Wei Lin

Chen-Hsiang Lu

Hui-Min Wang

Hung-Sui Lin

Yi-Chun Lin

Jin-Fu Lin

Chun-Cheng Liu

Tien-Chih Cheng

Syuan-Yi Chen

Che-Hsun Kuo

Po-Ying Chen

Chih-Hsun Chou

Tzu-Hua Lin

Tieh-Yen Chang

Ren-guan Duan

Lai Tu

Yen-Chi Chen

Jih-Ren Goh

Yuan-Tse Yu

Ching-Yuan Lin

Yen Long Lee

Ming-Liang Chung

Tz-Jing Shau

Xin-Ying Lin

Yu-Po Cheng

A fluorine-containing elastomer composition includes a curable fluorine-containing polymer comprising at least one fluorinated cure site monomer having a cure site; an group IIIB element-containing reinforcing additive in an amount of 8 to 15 weight parts with respect to 100 weight parts of the curable fluorine-containing polymer; and a curative configured for curing the at least one fluorinated cure site monomer.

Fluorine-containing elastomer composition and method for making cured fluorine-containing elastomer composition

A clock and data recovery (CDR) circuit is provided. A phase detection circuit receives an input signal and a clock signal to output a first voltage signal. A first comparing circuit determines whether the first voltage signal is within a voltage range to output a first up signal and a first down signal. A counting circuit updates a counting value according to the input signal and the clock signal. A second comparing circuit determines whether the counting value is within a value range to output a second up signal and a second down signal. A selection circuit outputs a second voltage signal according to the first up signal, the first down signal, the second up signal, and the second down signal. A voltage controlled oscillator outputs the clock signal according to the first voltage signal and the second voltage signal.

Clock and data recovery circuit with bidirectional frequency detection and electronic device using the same

A transmission control method for a vehicular ad hoc network system having a plurality of mobile nodes is provided. The mobile nodes include a source node, a destination node, and a plurality of relay nodes. The source node transmits a data packet to the destination node through the relay nodes. The method includes each mobile node capturing mobility information being periodically broadcasted from neighboring mobile nodes to correspondingly update the connection state table thereof, wherein the connection state table records the coverage remaining time between the mobile node and neighboring mobile nodes; when any of relay nodes determines that the coverage remaining time between the relay node and the subsequent mobile node is less than a predefined threshold, the relay node transforms into a proxy node, stores the data packet, and establishes a reliable sub-connection between the proxy node and a next proxy node or the destination node.

Transmission control method and communication apparatus using the same for vehicular ad hoc network system

A switched capacitor circuit with feedback compensation is provided. First terminals of a feedback capacitor and at least one capacitor are coupled to a first input terminal of a differential amplifier. Second terminals of the feedback capacitor and the capacitor are coupled to an input terminal during a first period. A feedback compensation circuit amplifies a first voltage on the first input terminal of the differential amplifier by a gain greater than one to generate a second voltage. The second terminal of the feedback capacitor is coupled to the output terminal of the differential amplifier, and the feedback compensation circuit applies the second voltage to the second terminal of the capacitor during a second period.

Switched capacitor circuit and compensation method thereof, and analog to digital converter

A clock and data recovery circuit and a method for estimating jitter tolerance thereof are provided. A first phase signal is generated by a phase detector, and a second phase signal is used to generate a clock signal. The second phase signal is set to be identical to the first phase signal during an operation mode. A counting is started and the first phase signal is inversed to generate the second phase signal during a test mode. Whether a data signal has an error is determined. The counting is stopped to generate a count value when determining that the data signal has the error during the test mode. A tracing speed is computed according to the count value and a predetermined unit interval.

Clock and data recovery circuit and method for estimating jitter tolerance thereof

A data relay mobile apparatus and a data relay method for a wireless network and a computer program product thereof are provided. The wireless network comprises a first mobile node and a second mobile node. The data relay mobile apparatus receives first status information and second status information from the first mobile node and the second mobile node, respectively. The data relay apparatus relays data according to the first status information and the second status information. With the aforesaid method, the present invention can effectively reduce the problems caused from shadow fading.

Data relay mobile apparatus, data relay method, and computer program product thereof for a wireless network

Disclosed herein are an apparatus and a method for warning of vehicle collision. The positioning and state-reporting signal of a present vehicle is sensed and that of a target vehicle received. The signals are respectively converted to velocities. The relative velocity of the vehicles and the relative position of the vehicles after a time interval are obtained. The driver of the present vehicle is warned when the normal distance from the present vehicle to the line indicating the direction of the relative velocity is determined to be at a minimum and not greater than a warning distance.

Vehicle collision warning apparatus and method

A duobinary voltage-mode transmitter comprises a first branch including a first logic circuit and a first driver, and a second branch including a second logic circuit and a second driver. When a transition occurs between NRZ signals, two ends of a first match circuit are electrically coupled between the output nodes of the first driver and the second driver, respectively, and the first driver and the second driver are turned off.

Duobinary voltage-mode transmitter

An adaptive switched-capacitor equalizer includes a first variable capacitor that is switchably connected between an input voltage and an output voltage, and a second variable capacitor that is switchably connected between the input voltage and the output voltage. The equalizer operates in a sequence of three phases, in a first phase of which the first variable is reset; in a second phase of which the first variable capacitor and the second variable capacitor are electrically connected in parallel between the input voltage and the output voltage; in a third phase of which calibration is performed according to the input voltages received in sequence.

Adaptive switched-capacitor equalizer

A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator coupled to receive a sampled input voltage; a pair of arrays each including individually switchable binary-weighted capacitors that are switchably coupled to an output of the comparator via phase switches, respectively. A phase signal for controlling a corresponding phase switch associated with a current bit becomes asserted when a preceding bit finishes comparison, and the phase signal becomes de-asserted when the current bit finishes comparison.

Asynchronous successive approximation register ADC

A method for transmitting data stream includes the steps of analyzing a request to generate a transmitting command, calculating a data receiving ability of a receiving end when receiving the transferring command, calculating an I frame dividing rate, a P frame dividing rate, and a B frame dividing rate based on the data receiving ability, dividing an I frame, a P frame, and a B frame based on the I frame dividing rate, the P frame dividing rate, and the B frame dividing rate to generate a plurality of I frame segments, P frame segments, and B frame segments, transmitting the I frame segments, P frame segments, and B frame segments of the data stream to the receiving end in turn base on the data receiving ability.

Method for transferring data stream

A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.

Successive approximation analog to digital converter with a direct switching technique for capacitor array through comparator output and method thereof

A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Clock and data recovery (CDR) architecture and phase detector thereof

A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

Successive approximation register ADC with a window predictive function

A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.

Growing community of inventors

Tainan, Taiwan

Chung-Ming Huang