Winbond Electronics Corporation

Other

Kabushiki Kaisha Toshiba

Fujitsu Corporation

Advance Furnace Systems Corp.

Chung-Ming Chu

Min-Chieh Yang

Ming-Chung Chiang

Katsuhiko Hieda

Toshiya Suzuki

Jun Lin

Bor-Ru Sheu

Wen-Shun Lo

Tu-Hao Yu

Wen-Chung Liu

Chih-Jung Ni

Haochieh Liu

Kuo-Chen Wang

Jong-Bor Wang

Pai-Hsuan Sun

Bor-Bu Sheu

A manufacturing method of common mode filters and a structure of the same are revealed. A common mode choke layer is disposed over a composite substrate and a second magnetic material layer is coated on an upper surface of the common mode choke layer. The common mode choke layer is produced by a wafer-level electrode leading out method and having leading-out terminals on sides thereof. External electrodes are formed on sides of the common mode choke layer by partial cutting, sputtering, lithography and electroplating at wafer level and corresponding to the leading-out terminals. Thereby common mode filters produced are supported more stably. Moreover, the volume is minimized due to inductive coils and external electrodes connected by wafer level packaging. Thus the common mode filters are mass-produced, the cost is down and the defect rate is reduced.

Manufacturing method of common mode filter

A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.

Capacitor

A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.

Flash memory cell and fabrication thereof

The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

Memory-storage node and the method of fabricating the same

A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.

Method of fabricating ruthenium-based contact plug for memory devices

Growing community of inventors

Hsinchu, Taiwan

Chung-Ming Chu