Winbond Electronics Corporation

Windbond Electronics Corp.

Chung-Meng Huang

Im-Cheol Ha

A memory controller for controlling a flash memory is provided. The memory controller includes a control circuit and a voltage generator. The control circuit is configured to program one or more pages of the flash memory in sequence, wherein each page includes a plurality of bytes. The voltage generator is configured to adjust the output voltage according to the control signal from the control circuit. The control circuit performs a programming verification operation on each byte of a current page of the one or more pages in a page programming mode, and calculates the first number of bytes which fail the programming verification operation and performs a programming operation again. The control circuit determines the programming mode of the page after the current page as the page programming mode or the byte programming mode according to the first number.

Memory controller and method for adaptively programming flash memory

A memory device includes a memory array and a frequency-to-voltage converter. The memory array includes a plurality of memory cells arranged in rows and columns, and gates of the memory cells in the same row are coupled to each other and connected to a word line. The frequency-to-voltage converter coupled between the word line and a clock signal source outside the memory device receives a clock signal, and correspondingly outputs different voltages to the word line in accordance with the frequency of the clock signal.

Memory device and control method thereof

A memory device and a control method for a non-volatile memory are provided. The non-volatile memory includes a target erasing region and an unselected region. The control method includes: erasing a target memory cell in the target erasing region. The unselected region is a region, excluding the target erasing region, in the non-volatile memory. The step of erasing the target memory cell includes an erasing operation, a verification operation, and an erasing loop after failing to pass the verification operation. The number of times of performing the erasing loop is an integer greater than or equal to 0. The control method further includes: refreshing a pre-defined portion in the unselected region, wherein a capacity of the pre-defined portion is determined by the number of times of performing the erasing loop.

Memory device and control method for performing refresh operation based on erasing loop number

Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually.

Over-erase verification and repair methods for flash memory

A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages. The sensing circuit comprises a reference voltage generator which includes a number of serial connected resistive devices and provides several reference voltages by voltage division; a data saving circuit outputs a data voltage; a comparing circuit compares the data voltage with the several reference voltages to output a comparing signal; a decoder receives and then decodes the comparing signal to output the data.

Sensing circuit for multi-level flash memory

A charge pump circuit is provided. The charge pump circuit includes a plurality of voltage-boosting stages connected in series with each other and having a supply terminal, a control terminal, and an output terminal respectively, and a plurality of voltage multipliers, each multiplier having an input terminal, a first output terminal for outputting a first clock signal, and a second output terminal for outputting a second clock signal respectively, wherein the input terminal of a first voltage multiplier is coupled to a clock signal, a magnitude of the first clock signal is a multiple of a magnitude of the second clock signal, each of the voltage multipliers is coupled the respective second output terminal thereof to the input terminal of a downstream voltage multiplier, and the first output terminal of the voltage multiplier is coupled to the control terminal of a respective one of the voltage-boosting stages.

Charge pump circuit with voltage multiplier for boosting clock signal and method thereof

The present invention provides a stack-gate flash memory array. In the present invention, one bit line for a conventional memory cell had been divided two independent bit lines; two word lines have been combined together via the gate terminal of an isolated transistor. Because the bit lines are divided and the word lines will stop the leakage current via the isolated transistor, the leakage current would not affect the other memory cells. Hence, the present invention can avoid the data inaccuracy due to the leakage current resulting from the erratic bits, and thus can extend the flash memory's lifetime.

Stack-gate flash memory array

The present invention discloses an NMOS coupling circuit for preventing gate junction breakdown of a flash memory. The present invention adds at least one isolating stage between a conducting stage and a high voltage HV of the prior coupling circuit, and the addition generates a benefit that the voltage difference of the high voltage HV is burdened by both the conducting stage and the isolating stage of the coupling circuit. In other words, the voltage difference in the gate junction of the conducting stage will be reduced, and the probability of punching through a transistor will also be reduced. For reducing the effect of an instant voltage difference when the high voltage HV is enabled, the present invention electrically connects one end of a diode to the gate of the isolating stage, and electrically connects another end of the diode to a lower power source VDD. Therefore, the magnitude of the VDD will be reduced from the instant voltage difference to protect the isolating stage from damaging when the high voltage HV is enabled.

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Hsinchu, Taiwan

Chung-Meng Huang