International Business Machines Corporation

Globalfoundries Inc.

Chung-Lung K Shum

Michael K Gschwind

Valentina Salapura

Timothy John Slegel

Fadi Y Busaba

Christian Jacobi

Eric M Schwarz

Maged M Michael

Anthony Saporito

Brian Robert Prasky

Jonathan D Bradbury

Christopher A Krygowski

Steven R Carlough

Dan F Greiner

Harold Wade Cain, Iii

Aaron Tsai

Charles Franklin Webb

Giles R Frazier

Charles W Gainey, Jr

Mark S Farrell

Bruce C Giamei

Marcel Mitran

David S Hutton

Kathryn Marie Jackson

James J Bonanno

Martin Recktenwald

Khary J Alexander

Barry Watson Krumm

Ulrich Mayer

John G Rell, Jr

Brian David Barrick

Kevin Alexander Stoodley

Jane Helen Bartik

Jennifer A Navarro

Christian Zoellin

Scott Barnett Swaney

Wolfgang Gellerich

Martin Schwidefsky

Michael H Wood

Younes Manton

Donald W Schmidt

Gregory William Alexander

Adam B Collura

Mark Anthony Check

Jonathan T Hsieh

Edward Thomas Malley

Daniel V Rosa

Damian Leo Osisek

Pak-kin Mak

Craig Raymond Walters

Hans-Werner Tast

Bradley Nelson

David Andrew Schroter

Michael Billeci

Kai Oliver Weber

Dean G Bair

James R Mitchell

Jang-Soo Lee

Joran S C Siu

Nicholas C Matsakis

William Vincent Huott

Erwin F Pfeffer

Frank Siegfried Lehnert

Patrick M West, Jr

John Stephen Liptay

Wen H Li

Thomas G Koehler

Timothy J Siegel

Guenter Gerwig

Derek E Williams

Alper Buyuktosunoglu

Lisa Cranton Heller

Patrick James Meaney

Viresh Paruthi

Wolfgang Roesner

Michael F Fee

Gustav E Sittmann, Iii

Elpida Tzortzatos

Phil C Yeh

Markus Kaltenbach

Stephen Gerard Shuma

Ute Gaertner

Timothy Carl Bronson

Kattamuri Ekanadham

Robert Alan Cargnoni

Bernd Nerz

Tobias Webel

Michael J Cadigan, Jr

Timothy Gerard McNamara

Stefan Payer

Alvan Wing Ng

Bodo Hoppe

Eyal Naor

Benedikt Geukes

Pawel Owczarczyk

Ali S El-Zein

Joerg Deutschle

Rebecca S Wisniewski

Richard Esten Bohn

Thomas Fuchs

A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Logical clock connection in an integrated circuit design

Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Error protection analysis of an integrated circuit

A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.

In-memory trace with overlapping processing and logout

Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

Using a shadow copy of a cache in a cache hierarchy

A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Reducing cache transfer overhead in a system

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Method to limit the time a semiconductor device operates above a maximum operating voltage

Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.

Temporarily suppressing processing of a restrained storage operand request

Aspects of branch prediction are suppressed for branch instructions executing in a transaction, of a transactional memory environment, that is a re-execution of a previously aborted transaction.

Suppressing branch prediction updates until forward progress is made in execution of a previously aborted transaction

An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

Latent modification instruction for substituting functionality of instructions during transactional execution

A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task and storing the task-relating branch prediction data of the second task in the branch prediction history table.

Method for maintaining a branch prediction history table

A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.

Store instruction to store instruction dependency

Effectiveness of prefetch instructions is determined. A prefetch instruction is executed to request that data be fetched into a cache of the computing environment. The effectiveness of the prefetch instruction is determined. This includes updating, based on executing the prefetch instruction, a cache directory of the cache. The updating includes, in the cache directory, effectiveness data relating to the data. The effectiveness data includes whether the data was installed in the cache based on the prefetch instruction. Additionally, the determining the effectiveness includes obtaining at least a portion of the effectiveness data from the cache directory, and using the at least a portion of effectiveness data to determine the effectiveness of the prefetch instruction.

Determining the effectiveness of prefetch instructions

A reload multiple instruction is used to restore a set of architected registers saved by a spill multiple instruction. The reload multiple instruction is executed, and the executing includes determining the set of architected registers to be restored, which is specified by the reload multiple instruction. The set of architected registers is restored from a selected snapshot that maps architected registers to physical registers. The restoring replaces one or more physical registers currently assigned to one or more architected registers of the set of architected registers with one or more physical registers of the selected snapshot corresponding to the set of architected registers.

Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination

Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization, and includes identifying a most utilized bus of a plurality of buses used for the prefetch of data, and monitoring utilization of the most utilized bus. The determination whether the rate of prefetching is to be changed is based on the monitoring. Based on determining that the rate is to be changed, the rate of prefetching is changed.

Controlling a rate of prefetching based on bus bandwidth

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Wappingers Falls, NY, United States of America

Chung-Lung K Shum