Siliconware Precision Industries Co., Ltd.

Chung-Lun Liu

Chin-Huang Chang

Jung-Pin Huang

Chien-Ping Huang

Chin-Tien Chiu

Cheng-Hsu Hsiao

Yi-Feng Chang

Jung-Ping Huang

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

Method for fabricating multi-chip stack structure

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.

Multi-chip stack structure and method for fabricating the same

A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

Fabrication method of multi-chip stack structure

Multi-chip stack structure and fabrication method thereof

A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.

Method for fabricating semiconductor package with stacked chips

A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Method for fabricating a warpage-preventive circuit board

Semiconductor package with stacked chips and method for fabricating the same

A multi-chip module is proposed, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. The multi-chip module is characterized by the use of adhesive with fillers to allow the topmost chip (i.e. the second chip) superimposed to the bottommost chip (i.e. the first chip) after the first chip electrically connected to the chip carrier. The thickness of the adhesive layer depends on the diameter of the fillers higher than loop height of the bonding wires that is positioned above the active surface of the first chip to prevent the bonding wires connected to the first chip to come in contact with the overlaid chip.

Multichip module

A warpage-preventive circuit board and method for fabricating the same is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Growing community of inventors

Taichung Hsien, Taiwan

Chung-Lun Liu