Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-Long Chang

Syun-Ming Jang Jang

Chih-Ping Chao

Tsung-Yu Yang

Chen-Hua Douglas Yu

Chun-Hung Chen

Ching-Chung Hsu

Kuan-Chi Tsai

Wei-Kung Tsai

Chia-Yi Chen

Kuo-Yu Cheng

Tsu Shih

Shyh-Chyi Wong

Jui-Yu Chang

David Ding-Chung Lu

Keng-Yu Chen

Cheng-Yuan Tsai

Jeng-Horng Chen

Cheng-Chieh Hsieh

Jye-Yen Cheng

Yu-Liang Lin

Chen-Fa Lu

Chun-Hon Chen

Hung-Chi Li

Chun-Hong Chen

Grace Chang

Che-Yung Lin

Chung-Shi Liu

Ying-Ho Chen

Denny Tang

Hua-Chou Tseng

Wen-Chin Lin

Li-Shyue Lai

Henry Lo

Chao-Chieh Tsai

Shwangming Jeng

Chaochieh Tsai

I-Lu Wu

Wei-Chun Hua

Yi-Sin Wang

Shao-Yu Chen

Shang-Ting Tsai

Chen-Yao Tang

Hsiang-Chi Chen

Yu Hung Chen

Cheng-Chang Hsu

Yueh-You Chen

Harry-Hak-Lay Chuang

Jin-Yuan Lee

Li-Jui Chen

Tien-I Bao

Ying-Lang Wang

Hun-Jan Tao

Mei Sheng Zhou

Cheng-Lin Huang

Chii-Ming M Wu

Wai-Yi Lien

Ming-Huan Tsai

Shine Chung

Chu-Yun Fu

Szu-An Wu

Ming-Shih Yeh

Chun-Hsien Lin

Ying-Chen Chao

Alex Kalnitsky

Ai-Sen Liu

Jyh-Chyurn Guo

Cheng-Yeh Shih

Wen-Kung Cheng

Jane-Bai Lai

Yong-En Syu

Juing-Yi Cheng

Chun-Ching Tsan

Hui-Ling Wang

Yung-Chih Tsai

So Wein Kuo

Jui-Cheng Lo

John Chern

Ju-Yu Chang

Shih Che Wang

Lung-Hsiang Chuang

Hua-Chao Tseng

Gorge Huang

Tony Lu

Gnesh Yeh

Candy Liang

Sunny Su

The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.

Semiconductor structure with ultra thick metal and manufacturing method thereof

A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Integrated circuit

The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Multi-terminal inductor for integrated circuit

An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Integrated circuit and manufacturing method thereof

A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.

Method of forming capacitor structure

Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

Semiconductor device and method for forming the same

A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Mechanisms for forming radio frequency (RF) area of integrated circuit structure

An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Integrated circuit using deep trench through silicon (DTS)

The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

Handle wafer for high resistivity trap-rich SOI

Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.

Protection structure for metal-oxide-metal capacitor

Growing community of inventors

Dou-Liu, Taiwan

Chung-Long Chang