Applied Materials, Inc.

Chung Liu

Hui Sun

Andrew Nguyen

Philip Allan Kraus

Xianmin Tang

Tza-Jing Gung

Yu Lei

Tae Hong Ha

Xuesong Lu

Yufei Hu

Kuan-Ting Liu

Shahid Rauf

Qian Fu

Meihua Shen

Sunil Srinivasan

Benjamin Schwarz

Jason Andrew Kenney

Nicolas Gani

Radhika C Mani

Hun Sang Kim

Noel Sun

Shinichi Koseki

Michael Nichols

Eda Tuncel

Abhijeet S Bagal

Dai-Wen Tang

Hyungje Woo

Shreeram Jyoti Dash

Deyang Li

Aaron Eppler

Yi-Chuan Chou

Olivier P Joubert

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

Directional selective junction clean with field polymer protections

Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing. The ability to synchronize and control waveform characteristics of a voltage waveform bias established on a substrate during processing allows for an improved control of the generated plasma and process of forming, for example, high-aspect ratio features in the surface of the substrate by a reactive ion etching process. As a result, greater precision for plasma processing can be achieved, which is described herein in more detail.

Reducing aspect ratio dependent etch with direct current bias pulsing

Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.

Selective carbon deposition on top and bottom surfaces of semiconductor substrates

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH&#x2014;NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are&#x2014;etched only minimally or not at all.

Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.

Methods for manufacturing a spacer with desired profile in an advanced patterning process

Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.

Methods for in-situ chamber clean utilized in an etching processing chamber

A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask.

Selective self-aligned double patterning of regions in an integrated circuit device

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Foster City, CA, United States of America

Chung Liu